cpu.h (88ce6c6ee85d902f59dc65afc3ca86b34f02b9ed) cpu.h (4426d3617d64922d97b74ed22e67e33b6fb7de0a)
1/*
2 * ARM virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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861 uint32_t id_isar3;
862 uint32_t id_isar4;
863 uint32_t id_isar5;
864 uint32_t id_isar6;
865 uint32_t mvfr0;
866 uint32_t mvfr1;
867 uint32_t mvfr2;
868 uint32_t id_dfr0;
1/*
2 * ARM virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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861 uint32_t id_isar3;
862 uint32_t id_isar4;
863 uint32_t id_isar5;
864 uint32_t id_isar6;
865 uint32_t mvfr0;
866 uint32_t mvfr1;
867 uint32_t mvfr2;
868 uint32_t id_dfr0;
869 uint32_t dbgdidr;
869 uint64_t id_aa64isar0;
870 uint64_t id_aa64isar1;
871 uint64_t id_aa64pfr0;
872 uint64_t id_aa64pfr1;
873 uint64_t id_aa64mmfr0;
874 uint64_t id_aa64mmfr1;
875 uint64_t id_aa64mmfr2;
876 uint64_t id_aa64dfr0;

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888 uint32_t id_afr0;
889 uint32_t id_mmfr0;
890 uint32_t id_mmfr1;
891 uint32_t id_mmfr2;
892 uint32_t id_mmfr3;
893 uint32_t id_mmfr4;
894 uint64_t id_aa64afr0;
895 uint64_t id_aa64afr1;
870 uint64_t id_aa64isar0;
871 uint64_t id_aa64isar1;
872 uint64_t id_aa64pfr0;
873 uint64_t id_aa64pfr1;
874 uint64_t id_aa64mmfr0;
875 uint64_t id_aa64mmfr1;
876 uint64_t id_aa64mmfr2;
877 uint64_t id_aa64dfr0;

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889 uint32_t id_afr0;
890 uint32_t id_mmfr0;
891 uint32_t id_mmfr1;
892 uint32_t id_mmfr2;
893 uint32_t id_mmfr3;
894 uint32_t id_mmfr4;
895 uint64_t id_aa64afr0;
896 uint64_t id_aa64afr1;
896 uint32_t dbgdidr;
897 uint32_t clidr;
898 uint64_t mp_affinity; /* MP ID without feature bits */
899 /* The elements of this array are the CCSIDR values for each cache,
900 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
901 */
902 uint32_t ccsidr[16];
903 uint64_t reset_cbar;
904 uint32_t reset_auxcr;

--- 2822 unchanged lines hidden --- 		897 uint32_t clidr;
898 uint64_t mp_affinity; /* MP ID without feature bits */
899 /* The elements of this array are the CCSIDR values for each cache,
900 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
901 */
902 uint32_t ccsidr[16];
903 uint64_t reset_cbar;
904 uint32_t reset_auxcr;

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