cpu.h (7f9e25a6e43356d4a0fb2cc201c1a45c5be5bb6c) | cpu.h (073011612b44771190bc091e459d0642d46c69b5) |
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1/* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either --- 191 unchanged lines hidden (view full) --- 200 * the two execution states, and means we do not need to explicitly 201 * map these registers when changing states. 202 * 203 * Align the data for use with TCG host vector operations. 204 */ 205 206#ifdef TARGET_AARCH64 207# define ARM_MAX_VQ 16 | 1/* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either --- 191 unchanged lines hidden (view full) --- 200 * the two execution states, and means we do not need to explicitly 201 * map these registers when changing states. 202 * 203 * Align the data for use with TCG host vector operations. 204 */ 205 206#ifdef TARGET_AARCH64 207# define ARM_MAX_VQ 16 |
208void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); 209void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); 210void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); | |
211#else 212# define ARM_MAX_VQ 1 | 208#else 209# define ARM_MAX_VQ 1 |
213static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } 214static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { } 215static inline void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) { } | |
216#endif 217 218typedef struct ARMVectorReg { 219 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 220} ARMVectorReg; 221 222#ifdef TARGET_AARCH64 223/* In AArch32 mode, predicate registers do not exist at all. */ --- 3967 unchanged lines hidden --- | 210#endif 211 212typedef struct ARMVectorReg { 213 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 214} ARMVectorReg; 215 216#ifdef TARGET_AARCH64 217/* In AArch32 mode, predicate registers do not exist at all. */ --- 3967 unchanged lines hidden --- |