cpu.h (47576b94af5c406fc6521fb336fb5c12beeac3f8) cpu.h (962fcbf2efe57231a9f5df0ae0f40c05e35628ba)
1/*
2 * ARM virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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671/* These values map onto the return values for
672 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */
673typedef enum ARMPSCIState {
674 PSCI_ON = 0,
675 PSCI_OFF = 1,
676 PSCI_ON_PENDING = 2
677} ARMPSCIState;
678
1/*
2 * ARM virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

--- 662 unchanged lines hidden (view full) ---

671/* These values map onto the return values for
672 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */
673typedef enum ARMPSCIState {
674 PSCI_ON = 0,
675 PSCI_OFF = 1,
676 PSCI_ON_PENDING = 2
677} ARMPSCIState;
678
679typedef struct ARMISARegisters ARMISARegisters;
680
679/**
680 * ARMCPU:
681 * @env: #CPUARMState
682 *
683 * An ARM CPU core.
684 */
685struct ARMCPU {
686 /*< private >*/

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1579 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
1580 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
1581 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
1582 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
1583 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
1584 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
1585 ARM_FEATURE_V8,
1586 ARM_FEATURE_AARCH64, /* supports 64 bit mode */
681/**
682 * ARMCPU:
683 * @env: #CPUARMState
684 *
685 * An ARM CPU core.
686 */
687struct ARMCPU {
688 /*< private >*/

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1581 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
1582 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
1583 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
1584 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
1585 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
1586 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
1587 ARM_FEATURE_V8,
1588 ARM_FEATURE_AARCH64, /* supports 64 bit mode */
1587 ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */
1588 ARM_FEATURE_CBAR, /* has cp15 CBAR */
1589 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */
1590 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
1591 ARM_FEATURE_EL2, /* has EL2 Virtualization support */
1592 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
1589 ARM_FEATURE_CBAR, /* has cp15 CBAR */
1590 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */
1591 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
1592 ARM_FEATURE_EL2, /* has EL2 Virtualization support */
1593 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
1593 ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */
1594 ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */
1595 ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */
1596 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
1597 ARM_FEATURE_PMU, /* has PMU support */
1598 ARM_FEATURE_VBAR, /* has cp15 VBAR */
1599 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
1600 ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */
1601 ARM_FEATURE_SVE, /* has Scalable Vector Extension */
1594 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
1595 ARM_FEATURE_PMU, /* has PMU support */
1596 ARM_FEATURE_VBAR, /* has cp15 VBAR */
1597 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
1598 ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */
1599 ARM_FEATURE_SVE, /* has Scalable Vector Extension */
1602 ARM_FEATURE_V8_SHA512, /* implements SHA512 part of v8 Crypto Extensions */
1603 ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */
1604 ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */
1605 ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */
1606 ARM_FEATURE_V8_ATOMICS, /* ARMv8.1-Atomics feature */
1607 ARM_FEATURE_V8_RDM, /* implements v8.1 simd round multiply */
1608 ARM_FEATURE_V8_DOTPROD, /* implements v8.2 simd dot product */
1609 ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */
1600 ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */
1610 ARM_FEATURE_V8_FCMA, /* has complex number part of v8.3 extensions. */
1611 ARM_FEATURE_M_MAIN, /* M profile Main Extension */
1612};
1613
1614static inline int arm_feature(CPUARMState *env, int feature)
1615{
1616 return (env->features & (1ULL << feature)) != 0;
1617}
1618

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3154static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
3155{
3156 return &env->vfp.zregs[regno].d[0];
3157}
3158
3159/* Shared between translate-sve.c and sve_helper.c. */
3160extern const uint64_t pred_esz_masks[4];
3161
1601 ARM_FEATURE_M_MAIN, /* M profile Main Extension */
1602};
1603
1604static inline int arm_feature(CPUARMState *env, int feature)
1605{
1606 return (env->features & (1ULL << feature)) != 0;
1607}
1608

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3144static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
3145{
3146 return &env->vfp.zregs[regno].d[0];
3147}
3148
3149/* Shared between translate-sve.c and sve_helper.c. */
3150extern const uint64_t pred_esz_masks[4];
3151
3152/*
3153 * 32-bit feature tests via id registers.
3154 */
3155static inline bool isar_feature_aa32_aes(const ARMISARegisters *id)
3156{
3157 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0;
3158}
3159
3160static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id)
3161{
3162 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1;
3163}
3164
3165static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id)
3166{
3167 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0;
3168}
3169
3170static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id)
3171{
3172 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0;
3173}
3174
3175static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id)
3176{
3177 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0;
3178}
3179
3180static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id)
3181{
3182 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0;
3183}
3184
3185static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id)
3186{
3187 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0;
3188}
3189
3190static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
3191{
3192 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
3193}
3194
3195/*
3196 * 64-bit feature tests via id registers.
3197 */
3198static inline bool isar_feature_aa64_aes(const ARMISARegisters *id)
3199{
3200 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0;
3201}
3202
3203static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id)
3204{
3205 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1;
3206}
3207
3208static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id)
3209{
3210 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0;
3211}
3212
3213static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id)
3214{
3215 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0;
3216}
3217
3218static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id)
3219{
3220 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1;
3221}
3222
3223static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id)
3224{
3225 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0;
3226}
3227
3228static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id)
3229{
3230 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0;
3231}
3232
3233static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id)
3234{
3235 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0;
3236}
3237
3238static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id)
3239{
3240 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0;
3241}
3242
3243static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id)
3244{
3245 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0;
3246}
3247
3248static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id)
3249{
3250 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0;
3251}
3252
3253static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
3254{
3255 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
3256}
3257
3258static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
3259{
3260 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
3261}
3262
3263/*
3264 * Forward to the above feature tests given an ARMCPU pointer.
3265 */
3266#define cpu_isar_feature(name, cpu) \
3267 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); })
3268
3162#endif
3269#endif