cpu.h (283fc52ade85eb50141f3b8b85f82b07d016cb17) cpu.h (eb94284d0812b4e7c11c5d075b584100ac1c1b9a)
1/*
2 * ARM virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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192 * map these registers when changing states.
193 *
194 * Align the data for use with TCG host vector operations.
195 */
196
197#ifdef TARGET_AARCH64
198# define ARM_MAX_VQ 16
199void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
1/*
2 * ARM virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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192 * map these registers when changing states.
193 *
194 * Align the data for use with TCG host vector operations.
195 */
196
197#ifdef TARGET_AARCH64
198# define ARM_MAX_VQ 16
199void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
200void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
200#else
201# define ARM_MAX_VQ 1
202static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { }
201#else
202# define ARM_MAX_VQ 1
203static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { }
204static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { }
203#endif
204
205typedef struct ARMVectorReg {
206 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
207} ARMVectorReg;
208
209#ifdef TARGET_AARCH64
210/* In AArch32 mode, predicate registers do not exist at all. */

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942 uint64_t mp_affinity; /* MP ID without feature bits */
943 /* The elements of this array are the CCSIDR values for each cache,
944 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
945 */
946 uint64_t ccsidr[16];
947 uint64_t reset_cbar;
948 uint32_t reset_auxcr;
949 bool reset_hivecs;
205#endif
206
207typedef struct ARMVectorReg {
208 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
209} ARMVectorReg;
210
211#ifdef TARGET_AARCH64
212/* In AArch32 mode, predicate registers do not exist at all. */

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944 uint64_t mp_affinity; /* MP ID without feature bits */
945 /* The elements of this array are the CCSIDR values for each cache,
946 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
947 */
948 uint64_t ccsidr[16];
949 uint64_t reset_cbar;
950 uint32_t reset_auxcr;
951 bool reset_hivecs;
952
953 /*
954 * Intermediate values used during property parsing.
955 * Once finalized, the values should be read from ID_AA64ISAR1.
956 */
957 bool prop_pauth;
958 bool prop_pauth_impdef;
959
950 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
951 uint32_t dcz_blocksize;
952 uint64_t rvbar;
953
954 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */
955 int gic_num_lrs; /* number of list registers */
956 int gic_vpribits; /* number of virtual priority bits */
957 int gic_vprebits; /* number of virtual preemption bits */

--- 3146 unchanged lines hidden --- 		960 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
961 uint32_t dcz_blocksize;
962 uint64_t rvbar;
963
964 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */
965 int gic_num_lrs; /* number of list registers */
966 int gic_vpribits; /* number of virtual priority bits */
967 int gic_vprebits; /* number of virtual preemption bits */

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