cpu.c (f5e6786de4815751b0a3d2235c760361f228ea48) cpu.c (42bea956f6f7477c06186c7add62fa0107a27a9c)
1/*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2

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1272#endif
1273
1274static Property arm_cpu_cfgend_property =
1275 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
1276
1277static Property arm_cpu_has_vfp_property =
1278 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true);
1279
1/*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2

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1272#endif
1273
1274static Property arm_cpu_cfgend_property =
1275 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
1276
1277static Property arm_cpu_has_vfp_property =
1278 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true);
1279
1280static Property arm_cpu_has_vfp_d32_property =
1281 DEFINE_PROP_BOOL("vfp-d32", ARMCPU, has_vfp_d32, true);
1282
1280static Property arm_cpu_has_neon_property =
1281 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true);
1282
1283static Property arm_cpu_has_dsp_property =
1284 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true);
1285
1286static Property arm_cpu_has_mpu_property =
1287 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);

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1403 ? cpu_isar_feature(aa64_fp_simd, cpu)
1404 : cpu_isar_feature(aa32_vfp, cpu)) {
1405 cpu->has_vfp = true;
1406 if (!kvm_enabled()) {
1407 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property);
1408 }
1409 }
1410
1283static Property arm_cpu_has_neon_property =
1284 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true);
1285
1286static Property arm_cpu_has_dsp_property =
1287 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true);
1288
1289static Property arm_cpu_has_mpu_property =
1290 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);

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1406 ? cpu_isar_feature(aa64_fp_simd, cpu)
1407 : cpu_isar_feature(aa32_vfp, cpu)) {
1408 cpu->has_vfp = true;
1409 if (!kvm_enabled()) {
1410 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property);
1411 }
1412 }
1413
1414 if (cpu->has_vfp && cpu_isar_feature(aa32_simd_r32, cpu)) {
1415 cpu->has_vfp_d32 = true;
1416 if (!kvm_enabled()) {
1417 /*
1418 * The permitted values of the SIMDReg bits [3:0] on
1419 * Armv8-A are either 0b0000 and 0b0010. On such CPUs,
1420 * make sure that has_vfp_d32 can not be set to false.
1421 */
1422 if (!(arm_feature(&cpu->env, ARM_FEATURE_V8) &&
1423 !arm_feature(&cpu->env, ARM_FEATURE_M))) {
1424 qdev_property_add_static(DEVICE(obj),
1425 &arm_cpu_has_vfp_d32_property);
1426 }
1427 }
1428 }
1429
1411 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) {
1412 cpu->has_neon = true;
1413 if (!kvm_enabled()) {
1414 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property);
1415 }
1416 }
1417
1418 if (arm_feature(&cpu->env, ARM_FEATURE_M) &&

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1669 * This is an architectural requirement for AArch64; AArch32 is
1670 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1671 */
1672 error_setg(errp,
1673 "AArch64 CPUs must have both VFP and Neon or neither");
1674 return;
1675 }
1676
1430 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) {
1431 cpu->has_neon = true;
1432 if (!kvm_enabled()) {
1433 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property);
1434 }
1435 }
1436
1437 if (arm_feature(&cpu->env, ARM_FEATURE_M) &&

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1688 * This is an architectural requirement for AArch64; AArch32 is
1689 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1690 */
1691 error_setg(errp,
1692 "AArch64 CPUs must have both VFP and Neon or neither");
1693 return;
1694 }
1695
1696 if (cpu->has_vfp_d32 != cpu->has_neon) {
1697 error_setg(errp, "ARM CPUs must have both VFP-D32 and Neon or neither");
1698 return;
1699 }
1700
1701 if (!cpu->has_vfp_d32) {
1702 uint32_t u;
1703
1704 u = cpu->isar.mvfr0;
1705 u = FIELD_DP32(u, MVFR0, SIMDREG, 1); /* 16 registers */
1706 cpu->isar.mvfr0 = u;
1707 }
1708
1677 if (!cpu->has_vfp) {
1678 uint64_t t;
1679 uint32_t u;
1680
1681 t = cpu->isar.id_aa64isar1;
1682 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0);
1683 cpu->isar.id_aa64isar1 = t;
1684

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1710 uint64_t t;
1711 uint32_t u;
1712
1713 t = cpu->isar.id_aa64isar1;
1714 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0);
1715 cpu->isar.id_aa64isar1 = t;
1716

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