| cpu.c (9ac5df20f51fabcba0d902025df4bd7ea987c158) | cpu.c (7fbc6a403a0aab834e764fa61d81ed8586cfe352) |
|---|---|
| 1/* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 --- 279 unchanged lines hidden (view full) --- 288 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 289 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 290 } 291 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 292 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 293 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 294 } 295 | 1/* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 --- 279 unchanged lines hidden (view full) --- 288 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 289 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 290 } 291 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 292 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 293 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 294 } 295 |
| 296 if (arm_feature(env, ARM_FEATURE_VFP)) { | 296 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { |
| 297 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 298 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 299 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 300 } 301 /* Unlike A/R profile, M profile defines the reset LR value */ 302 env->regs[14] = 0xffffffff; 303 304 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; --- 701 unchanged lines hidden (view full) --- 1006 ns_status, 1007 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1008 } 1009 1010 if (flags & CPU_DUMP_FPU) { 1011 int numvfpregs = 0; 1012 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1013 numvfpregs = 32; | 297 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 298 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 299 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 300 } 301 /* Unlike A/R profile, M profile defines the reset LR value */ 302 env->regs[14] = 0xffffffff; 303 304 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; --- 701 unchanged lines hidden (view full) --- 1006 ns_status, 1007 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1008 } 1009 1010 if (flags & CPU_DUMP_FPU) { 1011 int numvfpregs = 0; 1012 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1013 numvfpregs = 32; |
| 1014 } else if (arm_feature(env, ARM_FEATURE_VFP)) { | 1014 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { |
| 1015 numvfpregs = 16; 1016 } 1017 for (i = 0; i < numvfpregs; i++) { 1018 uint64_t v = *aa32_vfp_dreg(env, i); 1019 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1020 i * 2, (uint32_t)v, 1021 i * 2 + 1, (uint32_t)(v >> 32), 1022 i, v); --- 1931 unchanged lines hidden --- | 1015 numvfpregs = 16; 1016 } 1017 for (i = 0; i < numvfpregs; i++) { 1018 uint64_t v = *aa32_vfp_dreg(env, i); 1019 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1020 i * 2, (uint32_t)v, 1021 i * 2 + 1, (uint32_t)(v >> 32), 1022 i, v); --- 1931 unchanged lines hidden --- |