| cpu.c (9719f125b803f4e0fda834cd74a60dfa4ca398e2) | cpu.c (7d8c283e10dd818457e7c6a0f729fb03857253ac) |
|---|---|
| 1/* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 --- 2055 unchanged lines hidden (view full) --- 2064 */ 2065 cpu->isar.id_aa64pfr1 = 2066 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 2067 } 2068#endif 2069 2070 if (tcg_enabled()) { 2071 /* | 1/* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 --- 2055 unchanged lines hidden (view full) --- 2064 */ 2065 cpu->isar.id_aa64pfr1 = 2066 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 2067 } 2068#endif 2069 2070 if (tcg_enabled()) { 2071 /* |
| 2072 * Don't report the Statistical Profiling Extension in the ID 2073 * registers, because TCG doesn't implement it yet (not even a 2074 * minimal stub version) and guests will fall over when they 2075 * try to access the non-existent system registers for it. | 2072 * Don't report some architectural features in the ID registers 2073 * where TCG does not yet implement it (not even a minimal 2074 * stub version). This avoids guests falling over when they 2075 * try to access the non-existent system registers for them. |
| 2076 */ | 2076 */ |
| 2077 /* FEAT_SPE (Statistical Profiling Extension) */ |
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| 2077 cpu->isar.id_aa64dfr0 = 2078 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); | 2078 cpu->isar.id_aa64dfr0 = 2079 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); |
| 2080 /* FEAT_TRF (Self-hosted Trace Extension) */ 2081 cpu->isar.id_aa64dfr0 = 2082 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0); 2083 cpu->isar.id_dfr0 = 2084 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0); 2085 /* Trace Macrocell system register access */ 2086 cpu->isar.id_aa64dfr0 = 2087 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0); 2088 cpu->isar.id_dfr0 = 2089 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0); 2090 /* Memory mapped trace */ 2091 cpu->isar.id_dfr0 = 2092 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0); 2093 /* FEAT_AMU (Activity Monitors Extension) */ 2094 cpu->isar.id_aa64pfr0 = 2095 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, AMU, 0); 2096 cpu->isar.id_pfr0 = 2097 FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0); 2098 /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ 2099 cpu->isar.id_aa64pfr0 = 2100 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0); 2101 /* FEAT_NV (Nested Virtualization) */ 2102 cpu->isar.id_aa64mmfr2 = 2103 FIELD_DP64(cpu->isar.id_aa64mmfr2, ID_AA64MMFR2, NV, 0); |
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| 2079 } 2080 2081 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 2082 * to false or by setting pmsav7-dregion to 0. 2083 */ 2084 if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) { 2085 cpu->has_mpu = false; 2086 cpu->pmsav7_dregion = 0; --- 306 unchanged lines hidden --- | 2104 } 2105 2106 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 2107 * to false or by setting pmsav7-dregion to 0. 2108 */ 2109 if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) { 2110 cpu->has_mpu = false; 2111 cpu->pmsav7_dregion = 0; --- 306 unchanged lines hidden --- |