cpu.c (42f6ed919325413392bea247a1e6f135deb469cd) cpu.c (276c6e813719568bdc9743e87ff8f42115006206)
1/*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2

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180
181 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
182 /* 64 bit CPUs always start in 64 bit mode */
183 env->aarch64 = 1;
184#if defined(CONFIG_USER_ONLY)
185 env->pstate = PSTATE_MODE_EL0t;
186 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
187 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
1/*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2

--- 171 unchanged lines hidden (view full) ---

180
181 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
182 /* 64 bit CPUs always start in 64 bit mode */
183 env->aarch64 = 1;
184#if defined(CONFIG_USER_ONLY)
185 env->pstate = PSTATE_MODE_EL0t;
186 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
187 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
188 /* Enable all PAC keys. */
189 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
190 SCTLR_EnDA | SCTLR_EnDB);
188 /* Enable all PAC instructions */
189 env->cp15.hcr_el2 |= HCR_API;
190 env->cp15.scr_el3 |= SCR_API;
191 /* and to the FP/Neon instructions */
192 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
193 /* and to the SVE instructions */
194 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
195 env->cp15.cptr_el[3] |= CPTR_EZ;

--- 2049 unchanged lines hidden --- 		191 /* Enable all PAC instructions */
192 env->cp15.hcr_el2 |= HCR_API;
193 env->cp15.scr_el3 |= SCR_API;
194 /* and to the FP/Neon instructions */
195 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
196 /* and to the SVE instructions */
197 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
198 env->cp15.cptr_el[3] |= CPTR_EZ;

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