cpu.c (2a609df87d9b886fd38a190a754dbc241ff707e8) cpu.c (4426d3617d64922d97b74ed22e67e33b6fb7de0a)
1/*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2

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2293 cpu->id_mmfr1 = 0x20000000;
2294 cpu->id_mmfr2 = 0x01202000;
2295 cpu->id_mmfr3 = 0x11;
2296 cpu->isar.id_isar0 = 0x00101111;
2297 cpu->isar.id_isar1 = 0x12112111;
2298 cpu->isar.id_isar2 = 0x21232031;
2299 cpu->isar.id_isar3 = 0x11112131;
2300 cpu->isar.id_isar4 = 0x00111142;
1/*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2

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2293 cpu->id_mmfr1 = 0x20000000;
2294 cpu->id_mmfr2 = 0x01202000;
2295 cpu->id_mmfr3 = 0x11;
2296 cpu->isar.id_isar0 = 0x00101111;
2297 cpu->isar.id_isar1 = 0x12112111;
2298 cpu->isar.id_isar2 = 0x21232031;
2299 cpu->isar.id_isar3 = 0x11112131;
2300 cpu->isar.id_isar4 = 0x00111142;
2301 cpu->dbgdidr = 0x15141000;
2301 cpu->isar.dbgdidr = 0x15141000;
2302 cpu->clidr = (1 << 27) | (2 << 24) | 3;
2303 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
2304 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
2305 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
2306 cpu->reset_auxcr = 2;
2307 define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
2308}
2309

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2366 cpu->id_mmfr1 = 0x20000000;
2367 cpu->id_mmfr2 = 0x01230000;
2368 cpu->id_mmfr3 = 0x00002111;
2369 cpu->isar.id_isar0 = 0x00101111;
2370 cpu->isar.id_isar1 = 0x13112111;
2371 cpu->isar.id_isar2 = 0x21232041;
2372 cpu->isar.id_isar3 = 0x11112131;
2373 cpu->isar.id_isar4 = 0x00111142;
2302 cpu->clidr = (1 << 27) | (2 << 24) | 3;
2303 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
2304 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
2305 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
2306 cpu->reset_auxcr = 2;
2307 define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
2308}
2309

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2366 cpu->id_mmfr1 = 0x20000000;
2367 cpu->id_mmfr2 = 0x01230000;
2368 cpu->id_mmfr3 = 0x00002111;
2369 cpu->isar.id_isar0 = 0x00101111;
2370 cpu->isar.id_isar1 = 0x13112111;
2371 cpu->isar.id_isar2 = 0x21232041;
2372 cpu->isar.id_isar3 = 0x11112131;
2373 cpu->isar.id_isar4 = 0x00111142;
2374 cpu->dbgdidr = 0x35141000;
2374 cpu->isar.dbgdidr = 0x35141000;
2375 cpu->clidr = (1 << 27) | (1 << 24) | 3;
2376 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
2377 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
2378 define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
2379}
2380
2381#ifndef CONFIG_USER_ONLY
2382static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)

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2434 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
2435 * table 4-41 gives 0x02101110, which includes the arm div insns.
2436 */
2437 cpu->isar.id_isar0 = 0x02101110;
2438 cpu->isar.id_isar1 = 0x13112111;
2439 cpu->isar.id_isar2 = 0x21232041;
2440 cpu->isar.id_isar3 = 0x11112131;
2441 cpu->isar.id_isar4 = 0x10011142;
2375 cpu->clidr = (1 << 27) | (1 << 24) | 3;
2376 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
2377 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
2378 define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
2379}
2380
2381#ifndef CONFIG_USER_ONLY
2382static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)

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2434 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
2435 * table 4-41 gives 0x02101110, which includes the arm div insns.
2436 */
2437 cpu->isar.id_isar0 = 0x02101110;
2438 cpu->isar.id_isar1 = 0x13112111;
2439 cpu->isar.id_isar2 = 0x21232041;
2440 cpu->isar.id_isar3 = 0x11112131;
2441 cpu->isar.id_isar4 = 0x10011142;
2442 cpu->dbgdidr = 0x3515f005;
2442 cpu->isar.dbgdidr = 0x3515f005;
2443 cpu->clidr = 0x0a200023;
2444 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
2445 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
2446 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
2447 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
2448}
2449
2450static void cortex_a15_initfn(Object *obj)

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2477 cpu->id_mmfr1 = 0x20000000;
2478 cpu->id_mmfr2 = 0x01240000;
2479 cpu->id_mmfr3 = 0x02102211;
2480 cpu->isar.id_isar0 = 0x02101110;
2481 cpu->isar.id_isar1 = 0x13112111;
2482 cpu->isar.id_isar2 = 0x21232041;
2483 cpu->isar.id_isar3 = 0x11112131;
2484 cpu->isar.id_isar4 = 0x10011142;
2443 cpu->clidr = 0x0a200023;
2444 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
2445 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
2446 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
2447 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
2448}
2449
2450static void cortex_a15_initfn(Object *obj)

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2477 cpu->id_mmfr1 = 0x20000000;
2478 cpu->id_mmfr2 = 0x01240000;
2479 cpu->id_mmfr3 = 0x02102211;
2480 cpu->isar.id_isar0 = 0x02101110;
2481 cpu->isar.id_isar1 = 0x13112111;
2482 cpu->isar.id_isar2 = 0x21232041;
2483 cpu->isar.id_isar3 = 0x11112131;
2484 cpu->isar.id_isar4 = 0x10011142;
2485 cpu->dbgdidr = 0x3515f021;
2485 cpu->isar.dbgdidr = 0x3515f021;
2486 cpu->clidr = 0x0a200023;
2487 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
2488 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
2489 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
2490 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
2491}
2492
2493static void ti925t_initfn(Object *obj)

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2487 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
2488 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
2489 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
2490 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
2491}
2492
2493static void ti925t_initfn(Object *obj)

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