cpu.c (0529245488865038344d64fff7ee05864d3d17f6) cpu.c (56c6c98df85cb03b1e72ef92111c4f9dde542d74)
1/*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2

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85 */
86 if (is_a64(env)) {
87 env->pc = tb_pc(tb);
88 } else {
89 env->regs[15] = tb_pc(tb);
90 }
91 }
92}
1/*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2

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85 */
86 if (is_a64(env)) {
87 env->pc = tb_pc(tb);
88 } else {
89 env->regs[15] = tb_pc(tb);
90 }
91 }
92}
93
94static void arm_restore_state_to_opc(CPUState *cs,
95 const TranslationBlock *tb,
96 const uint64_t *data)
97{
98 CPUARMState *env = cs->env_ptr;
99
100 if (is_a64(env)) {
101 if (TARGET_TB_PCREL) {
102 env->pc = (env->pc & TARGET_PAGE_MASK) | data[0];
103 } else {
104 env->pc = data[0];
105 }
106 env->condexec_bits = 0;
107 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT;
108 } else {
109 if (TARGET_TB_PCREL) {
110 env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0];
111 } else {
112 env->regs[15] = data[0];
113 }
114 env->condexec_bits = data[1];
115 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT;
116 }
117}
93#endif /* CONFIG_TCG */
94
95static bool arm_cpu_has_work(CPUState *cs)
96{
97 ARMCPU *cpu = ARM_CPU(cs);
98
99 return (cpu->power_state != PSCI_OFF)
100 && cs->interrupt_request &

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2147};
2148#endif
2149
2150#ifdef CONFIG_TCG
2151static const struct TCGCPUOps arm_tcg_ops = {
2152 .initialize = arm_translate_init,
2153 .synchronize_from_tb = arm_cpu_synchronize_from_tb,
2154 .debug_excp_handler = arm_debug_excp_handler,
118#endif /* CONFIG_TCG */
119
120static bool arm_cpu_has_work(CPUState *cs)
121{
122 ARMCPU *cpu = ARM_CPU(cs);
123
124 return (cpu->power_state != PSCI_OFF)
125 && cs->interrupt_request &

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2172};
2173#endif
2174
2175#ifdef CONFIG_TCG
2176static const struct TCGCPUOps arm_tcg_ops = {
2177 .initialize = arm_translate_init,
2178 .synchronize_from_tb = arm_cpu_synchronize_from_tb,
2179 .debug_excp_handler = arm_debug_excp_handler,
2180 .restore_state_to_opc = arm_restore_state_to_opc,
2155
2156#ifdef CONFIG_USER_ONLY
2157 .record_sigsegv = arm_cpu_record_sigsegv,
2158 .record_sigbus = arm_cpu_record_sigbus,
2159#else
2160 .tlb_fill = arm_cpu_tlb_fill,
2161 .cpu_exec_interrupt = arm_cpu_exec_interrupt,
2162 .do_interrupt = arm_cpu_do_interrupt,

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2182#ifdef CONFIG_USER_ONLY
2183 .record_sigsegv = arm_cpu_record_sigsegv,
2184 .record_sigbus = arm_cpu_record_sigbus,
2185#else
2186 .tlb_fill = arm_cpu_tlb_fill,
2187 .cpu_exec_interrupt = arm_cpu_exec_interrupt,
2188 .do_interrupt = arm_cpu_do_interrupt,

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