cpu.h (d8276573da58e8ce78dab8c46dd660efd664bcb7) cpu.h (21ba856499f9c0ccdc05ed04432df059ae76b337)
1/*
2 * Alpha emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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193#define SWCR_STATUS_INV (1U << 17)
194#define SWCR_STATUS_DZE (1U << 18)
195#define SWCR_STATUS_OVF (1U << 19)
196#define SWCR_STATUS_UNF (1U << 20)
197#define SWCR_STATUS_INE (1U << 21)
198#define SWCR_STATUS_DNO (1U << 22)
199#define SWCR_STATUS_MASK ((1U << 23) - (1U << 17))
200
1/*
2 * Alpha emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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193#define SWCR_STATUS_INV (1U << 17)
194#define SWCR_STATUS_DZE (1U << 18)
195#define SWCR_STATUS_OVF (1U << 19)
196#define SWCR_STATUS_UNF (1U << 20)
197#define SWCR_STATUS_INE (1U << 21)
198#define SWCR_STATUS_DNO (1U << 22)
199#define SWCR_STATUS_MASK ((1U << 23) - (1U << 17))
200
201#define SWCR_STATUS_TO_EXCSUM_SHIFT 16
202
201#define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK)
202
203/* MMU modes definitions */
204
205/* Alpha has 5 MMU modes: PALcode, Kernel, Executive, Supervisor, and User.
206 The Unix PALcode only exposes the kernel and user modes; presumably
207 executive and supervisor are used by VMS.
208

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230 float64 fir[31];
231 uint64_t pc;
232 uint64_t unique;
233 uint64_t lock_addr;
234 uint64_t lock_value;
235
236 /* The FPCR, and disassembled portions thereof. */
237 uint32_t fpcr;
203#define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK)
204
205/* MMU modes definitions */
206
207/* Alpha has 5 MMU modes: PALcode, Kernel, Executive, Supervisor, and User.
208 The Unix PALcode only exposes the kernel and user modes; presumably
209 executive and supervisor are used by VMS.
210

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232 float64 fir[31];
233 uint64_t pc;
234 uint64_t unique;
235 uint64_t lock_addr;
236 uint64_t lock_value;
237
238 /* The FPCR, and disassembled portions thereof. */
239 uint32_t fpcr;
240#ifdef CONFIG_USER_ONLY
241 uint32_t swcr;
242#endif
238 uint32_t fpcr_exc_enable;
239 float_status fp_status;
240 uint8_t fpcr_dyn_round;
241 uint8_t fpcr_flush_to_zero;
242
243 /* Mask of PALmode, Processor State et al. Most of this gets copied
244 into the TranslatorBlock flags and controls code generation. */
245 uint32_t flags;

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496static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
497 target_ulong *cs_base, uint32_t *pflags)
498{
499 *pc = env->pc;
500 *cs_base = 0;
501 *pflags = env->flags & ENV_FLAG_TB_MASK;
502}
503
243 uint32_t fpcr_exc_enable;
244 float_status fp_status;
245 uint8_t fpcr_dyn_round;
246 uint8_t fpcr_flush_to_zero;
247
248 /* Mask of PALmode, Processor State et al. Most of this gets copied
249 into the TranslatorBlock flags and controls code generation. */
250 uint32_t flags;

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501static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
502 target_ulong *cs_base, uint32_t *pflags)
503{
504 *pc = env->pc;
505 *cs_base = 0;
506 *pflags = env->flags & ENV_FLAG_TB_MASK;
507}
508
509#ifdef CONFIG_USER_ONLY
510/* Copied from linux ieee_swcr_to_fpcr. */
511static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr)
512{
513 uint64_t fpcr = 0;
514
515 fpcr |= (swcr & SWCR_STATUS_MASK) << 35;
516 fpcr |= (swcr & SWCR_MAP_DMZ) << 36;
517 fpcr |= (~swcr & (SWCR_TRAP_ENABLE_INV
518 | SWCR_TRAP_ENABLE_DZE
519 | SWCR_TRAP_ENABLE_OVF)) << 48;
520 fpcr |= (~swcr & (SWCR_TRAP_ENABLE_UNF
521 | SWCR_TRAP_ENABLE_INE)) << 57;
522 fpcr |= (swcr & SWCR_MAP_UMZ ? FPCR_UNDZ | FPCR_UNFD : 0);
523 fpcr |= (~swcr & SWCR_TRAP_ENABLE_DNO) << 41;
524
525 return fpcr;
526}
527
528/* Copied from linux ieee_fpcr_to_swcr. */
529static inline uint64_t alpha_ieee_fpcr_to_swcr(uint64_t fpcr)
530{
531 uint64_t swcr = 0;
532
533 swcr |= (fpcr >> 35) & SWCR_STATUS_MASK;
534 swcr |= (fpcr >> 36) & SWCR_MAP_DMZ;
535 swcr |= (~fpcr >> 48) & (SWCR_TRAP_ENABLE_INV
536 | SWCR_TRAP_ENABLE_DZE
537 | SWCR_TRAP_ENABLE_OVF);
538 swcr |= (~fpcr >> 57) & (SWCR_TRAP_ENABLE_UNF | SWCR_TRAP_ENABLE_INE);
539 swcr |= (fpcr >> 47) & SWCR_MAP_UMZ;
540 swcr |= (~fpcr >> 41) & SWCR_TRAP_ENABLE_DNO;
541
542 return swcr;
543}
544#endif /* CONFIG_USER_ONLY */
545
504#endif /* ALPHA_CPU_H */
546#endif /* ALPHA_CPU_H */