cpu.h (6d8e75d41c58892ccc5d4ad61c4da476684c1c83) cpu.h (74433bf083b0766aba81534f92de13194f23ff3e)
1/*
2 * Alpha emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef ALPHA_CPU_H
21#define ALPHA_CPU_H
22
23#include "qemu-common.h"
24#include "cpu-qom.h"
1/*
2 * Alpha emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef ALPHA_CPU_H
21#define ALPHA_CPU_H
22
23#include "qemu-common.h"
24#include "cpu-qom.h"
25#include "exec/cpu-defs.h"
25
26
26#define TARGET_LONG_BITS 64
27#define ALIGNED_ONLY
28
29#define CPUArchState struct CPUAlphaState
30
31/* Alpha processors have a weak memory model */
32#define TCG_GUEST_DEFAULT_MO (0)
33
27#define ALIGNED_ONLY
28
29#define CPUArchState struct CPUAlphaState
30
31/* Alpha processors have a weak memory model */
32#define TCG_GUEST_DEFAULT_MO (0)
33
34#include "exec/cpu-defs.h"
35
36#define ICACHE_LINE_SIZE 32
37#define DCACHE_LINE_SIZE 32
38
34#define ICACHE_LINE_SIZE 32
35#define DCACHE_LINE_SIZE 32
36
39#define TARGET_PAGE_BITS 13
40
41#ifdef CONFIG_USER_ONLY
42/* ??? The kernel likes to give addresses in high memory. If the host has
43 more virtual address space than the guest, this can lead to impossible
44 allocations. Honor the long-standing assumption that only kernel addrs
45 are negative, but otherwise allow allocations anywhere. This could lead
46 to tricky emulation problems for programs doing tagged addressing, but
47 that's far fewer than encounter the impossible allocation problem. */
48#define TARGET_PHYS_ADDR_SPACE_BITS 63
49#define TARGET_VIRT_ADDR_SPACE_BITS 63
50#else
51/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */
52#define TARGET_PHYS_ADDR_SPACE_BITS 44
53#define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS)
54#endif
55
56/* Alpha major type */
57enum {
58 ALPHA_EV3 = 1,
59 ALPHA_EV4 = 2,
60 ALPHA_SIM = 3,
61 ALPHA_LCA = 4,
62 ALPHA_EV5 = 5, /* 21164 */
63 ALPHA_EV45 = 6, /* 21064A */

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212 there are PALmode instructions that can access data via physical mode
213 or via an os-installed "alternate mode", which is one of the 4 above.
214
215 That said, we're only emulating Unix PALcode, and not attempting VMS,
216 so we don't need to implement Executive and Supervisor. QEMU's own
217 PALcode cheats and usees the KSEG mapping for its code+data rather than
218 physical addresses. */
219
37/* Alpha major type */
38enum {
39 ALPHA_EV3 = 1,
40 ALPHA_EV4 = 2,
41 ALPHA_SIM = 3,
42 ALPHA_LCA = 4,
43 ALPHA_EV5 = 5, /* 21164 */
44 ALPHA_EV45 = 6, /* 21064A */

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193 there are PALmode instructions that can access data via physical mode
194 or via an os-installed "alternate mode", which is one of the 4 above.
195
196 That said, we're only emulating Unix PALcode, and not attempting VMS,
197 so we don't need to implement Executive and Supervisor. QEMU's own
198 PALcode cheats and usees the KSEG mapping for its code+data rather than
199 physical addresses. */
200
220#define NB_MMU_MODES 3
221
222#define MMU_MODE0_SUFFIX _kernel
223#define MMU_MODE1_SUFFIX _user
224#define MMU_KERNEL_IDX 0
225#define MMU_USER_IDX 1
226#define MMU_PHYS_IDX 2
227
228typedef struct CPUAlphaState CPUAlphaState;
229

--- 317 unchanged lines hidden --- 		201#define MMU_MODE0_SUFFIX _kernel
202#define MMU_MODE1_SUFFIX _user
203#define MMU_KERNEL_IDX 0
204#define MMU_USER_IDX 1
205#define MMU_PHYS_IDX 2
206
207typedef struct CPUAlphaState CPUAlphaState;
208

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