| qemu-options.hx (9b12dfa03a94d7f7a4b54eb67229a31e58193384) | qemu-options.hx (c412a48d4d91e8f8b89aae02de0f44f1f0b729e5) |
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| 1HXCOMM Use DEFHEADING() to define headings in both help text and texi 2HXCOMM Text between STEXI and ETEXI are copied to texi version and 3HXCOMM discarded from C version 4HXCOMM DEF(option, HAS_ARG/0, opt_enum, opt_help, arch_mask) is used to 5HXCOMM construct option structures, enums and help message for specified 6HXCOMM architectures. 7HXCOMM HXCOMM can be used for comments, discarded from both texi and C 8 --- 162 unchanged lines hidden (view full) --- 171@var{maxcpus} specifies the maximum number of hotpluggable CPUs. 172ETEXI 173 174DEF("numa", HAS_ARG, QEMU_OPTION_numa, 175 "-numa node[,mem=size][,cpus=firstcpu[-lastcpu]][,nodeid=node][,initiator=node]\n" 176 "-numa node[,memdev=id][,cpus=firstcpu[-lastcpu]][,nodeid=node][,initiator=node]\n" 177 "-numa dist,src=source,dst=destination,val=distance\n" 178 "-numa cpu,node-id=node[,socket-id=x][,core-id=y][,thread-id=z]\n" | 1HXCOMM Use DEFHEADING() to define headings in both help text and texi 2HXCOMM Text between STEXI and ETEXI are copied to texi version and 3HXCOMM discarded from C version 4HXCOMM DEF(option, HAS_ARG/0, opt_enum, opt_help, arch_mask) is used to 5HXCOMM construct option structures, enums and help message for specified 6HXCOMM architectures. 7HXCOMM HXCOMM can be used for comments, discarded from both texi and C 8 --- 162 unchanged lines hidden (view full) --- 171@var{maxcpus} specifies the maximum number of hotpluggable CPUs. 172ETEXI 173 174DEF("numa", HAS_ARG, QEMU_OPTION_numa, 175 "-numa node[,mem=size][,cpus=firstcpu[-lastcpu]][,nodeid=node][,initiator=node]\n" 176 "-numa node[,memdev=id][,cpus=firstcpu[-lastcpu]][,nodeid=node][,initiator=node]\n" 177 "-numa dist,src=source,dst=destination,val=distance\n" 178 "-numa cpu,node-id=node[,socket-id=x][,core-id=y][,thread-id=z]\n" |
| 179 "-numa hmat-lb,initiator=node,target=node,hierarchy=memory|first-level|second-level|third-level,data-type=access-latency|read-latency|write-latency[,latency=lat][,bandwidth=bw]\n", | 179 "-numa hmat-lb,initiator=node,target=node,hierarchy=memory|first-level|second-level|third-level,data-type=access-latency|read-latency|write-latency[,latency=lat][,bandwidth=bw]\n" 180 "-numa hmat-cache,node-id=node,size=size,level=level[,associativity=none|direct|complex][,policy=none|write-back|write-through][,line=size]\n", |
| 180 QEMU_ARCH_ALL) 181STEXI 182@item -numa node[,mem=@var{size}][,cpus=@var{firstcpu}[-@var{lastcpu}]][,nodeid=@var{node}][,initiator=@var{initiator}] 183@itemx -numa node[,memdev=@var{id}][,cpus=@var{firstcpu}[-@var{lastcpu}]][,nodeid=@var{node}][,initiator=@var{initiator}] 184@itemx -numa dist,src=@var{source},dst=@var{destination},val=@var{distance} 185@itemx -numa cpu,node-id=@var{node}[,socket-id=@var{x}][,core-id=@var{y}][,thread-id=@var{z}] 186@itemx -numa hmat-lb,initiator=@var{node},target=@var{node},hierarchy=@var{hierarchy},data-type=@var{tpye}[,latency=@var{lat}][,bandwidth=@var{bw}] | 181 QEMU_ARCH_ALL) 182STEXI 183@item -numa node[,mem=@var{size}][,cpus=@var{firstcpu}[-@var{lastcpu}]][,nodeid=@var{node}][,initiator=@var{initiator}] 184@itemx -numa node[,memdev=@var{id}][,cpus=@var{firstcpu}[-@var{lastcpu}]][,nodeid=@var{node}][,initiator=@var{initiator}] 185@itemx -numa dist,src=@var{source},dst=@var{destination},val=@var{distance} 186@itemx -numa cpu,node-id=@var{node}[,socket-id=@var{x}][,core-id=@var{y}][,thread-id=@var{z}] 187@itemx -numa hmat-lb,initiator=@var{node},target=@var{node},hierarchy=@var{hierarchy},data-type=@var{tpye}[,latency=@var{lat}][,bandwidth=@var{bw}] |
| 188@itemx -numa hmat-cache,node-id=@var{node},size=@var{size},level=@var{level}[,associativity=@var{str}][,policy=@var{str}][,line=@var{size}] |
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| 187@findex -numa 188Define a NUMA node and assign RAM and VCPUs to it. 189Set the NUMA distance from a source node to a destination node. 190Set the ACPI Heterogeneous Memory Attributes for the given nodes. 191 192Legacy VCPU assignment uses @samp{cpus} option where 193@var{firstcpu} and @var{lastcpu} are CPU indexes. Each 194@samp{cpus} option represent a contiguous range of CPU indexes --- 87 unchanged lines hidden (view full) --- 282target memory side cache. 283 284@var{lat} is latency value in nanoseconds. @var{bw} is bandwidth value, 285the possible value and units are NUM[M|G|T], mean that the bandwidth value are 286NUM byte per second (or MB/s, GB/s or TB/s depending on used suffix). 287Note that if latency or bandwidth value is 0, means the corresponding latency or 288bandwidth information is not provided. 289 | 189@findex -numa 190Define a NUMA node and assign RAM and VCPUs to it. 191Set the NUMA distance from a source node to a destination node. 192Set the ACPI Heterogeneous Memory Attributes for the given nodes. 193 194Legacy VCPU assignment uses @samp{cpus} option where 195@var{firstcpu} and @var{lastcpu} are CPU indexes. Each 196@samp{cpus} option represent a contiguous range of CPU indexes --- 87 unchanged lines hidden (view full) --- 284target memory side cache. 285 286@var{lat} is latency value in nanoseconds. @var{bw} is bandwidth value, 287the possible value and units are NUM[M|G|T], mean that the bandwidth value are 288NUM byte per second (or MB/s, GB/s or TB/s depending on used suffix). 289Note that if latency or bandwidth value is 0, means the corresponding latency or 290bandwidth information is not provided. 291 |
| 292In @samp{hmat-cache} option, @var{node-id} is the NUMA-id of the memory belongs. 293@var{size} is the size of memory side cache in bytes. @var{level} is the cache 294level described in this structure, note that the cache level 0 should not be used 295with @samp{hmat-cache} option. @var{associativity} is the cache associativity, 296the possible value is 'none/direct(direct-mapped)/complex(complex cache indexing)'. 297@var{policy} is the write policy. @var{line} is the cache Line size in bytes. 298 |
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| 290For example, the following options describe 2 NUMA nodes. Node 0 has 2 cpus and 291a ram, node 1 has only a ram. The processors in node 0 access memory in node 2920 with access-latency 5 nanoseconds, access-bandwidth is 200 MB/s; 293The processors in NUMA node 0 access memory in NUMA node 1 with access-latency 10 294nanoseconds, access-bandwidth is 100 MB/s. | 299For example, the following options describe 2 NUMA nodes. Node 0 has 2 cpus and 300a ram, node 1 has only a ram. The processors in node 0 access memory in node 3010 with access-latency 5 nanoseconds, access-bandwidth is 200 MB/s; 302The processors in NUMA node 0 access memory in NUMA node 1 with access-latency 10 303nanoseconds, access-bandwidth is 100 MB/s. |
| 304And for memory side cache information, NUMA node 0 and 1 both have 1 level memory 305cache, size is 10KB, policy is write-back, the cache Line size is 8 bytes: |
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| 295@example 296-machine hmat=on \ 297-m 2G \ 298-object memory-backend-ram,size=1G,id=m0 \ 299-object memory-backend-ram,size=1G,id=m1 \ 300-smp 2 \ 301-numa node,nodeid=0,memdev=m0 \ 302-numa node,nodeid=1,memdev=m1,initiator=0 \ 303-numa cpu,node-id=0,socket-id=0 \ 304-numa cpu,node-id=0,socket-id=1 \ 305-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,latency=5 \ 306-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=200M \ 307-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,latency=10 \ | 306@example 307-machine hmat=on \ 308-m 2G \ 309-object memory-backend-ram,size=1G,id=m0 \ 310-object memory-backend-ram,size=1G,id=m1 \ 311-smp 2 \ 312-numa node,nodeid=0,memdev=m0 \ 313-numa node,nodeid=1,memdev=m1,initiator=0 \ 314-numa cpu,node-id=0,socket-id=0 \ 315-numa cpu,node-id=0,socket-id=1 \ 316-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,latency=5 \ 317-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=200M \ 318-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,latency=10 \ |
| 308-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=100M | 319-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=100M \ 320-numa hmat-cache,node-id=0,size=10K,level=1,associativity=direct,policy=write-back,line=8 \ 321-numa hmat-cache,node-id=1,size=10K,level=1,associativity=direct,policy=write-back,line=8 |
| 309@end example 310 311ETEXI 312 313DEF("add-fd", HAS_ARG, QEMU_OPTION_add_fd, 314 "-add-fd fd=fd,set=set[,opaque=opaque]\n" 315 " Add 'fd' to fd 'set'\n", QEMU_ARCH_ALL) 316STEXI --- 4653 unchanged lines hidden --- | 322@end example 323 324ETEXI 325 326DEF("add-fd", HAS_ARG, QEMU_OPTION_add_fd, 327 "-add-fd fd=fd,set=set[,opaque=opaque]\n" 328 " Add 'fd' to fd 'set'\n", QEMU_ARCH_ALL) 329STEXI --- 4653 unchanged lines hidden --- |