main.c (a2aa09e18186801931763fbd40a751fa39971b18) main.c (b16189b22244e4cc158a3425b377b219586ec8ca)
1/*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or

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3407 exit(1);
3408 }
3409 process_pending_signals (env);
3410 }
3411}
3412
3413#endif /* TARGET_S390X */
3414
1/*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or

--- 3398 unchanged lines hidden (view full) ---

3407 exit(1);
3408 }
3409 process_pending_signals (env);
3410 }
3411}
3412
3413#endif /* TARGET_S390X */
3414
3415#ifdef TARGET_TILEGX
3416
3417static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
3418{
3419 target_siginfo_t info;
3420
3421 info.si_signo = TARGET_SIGSEGV;
3422 info.si_errno = 0;
3423 info.si_code = TARGET_SEGV_MAPERR;
3424 info._sifields._sigfault._addr = addr;
3425 queue_signal(env, info.si_signo, &info);
3426}
3427
3428static void gen_sigill_reg(CPUTLGState *env)
3429{
3430 target_siginfo_t info;
3431
3432 info.si_signo = TARGET_SIGILL;
3433 info.si_errno = 0;
3434 info.si_code = TARGET_ILL_PRVREG;
3435 info._sifields._sigfault._addr = env->pc;
3436 queue_signal(env, info.si_signo, &info);
3437}
3438
3439void cpu_loop(CPUTLGState *env)
3440{
3441 CPUState *cs = CPU(tilegx_env_get_cpu(env));
3442 int trapnr;
3443
3444 while (1) {
3445 cpu_exec_start(cs);
3446 trapnr = cpu_tilegx_exec(cs);
3447 cpu_exec_end(cs);
3448 switch (trapnr) {
3449 case TILEGX_EXCP_SYSCALL:
3450 env->regs[TILEGX_R_RE] = do_syscall(env, env->regs[TILEGX_R_NR],
3451 env->regs[0], env->regs[1],
3452 env->regs[2], env->regs[3],
3453 env->regs[4], env->regs[5],
3454 env->regs[6], env->regs[7]);
3455 env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(env->regs[TILEGX_R_RE])
3456 ? - env->regs[TILEGX_R_RE]
3457 : 0;
3458 break;
3459 case TILEGX_EXCP_REG_IDN_ACCESS:
3460 case TILEGX_EXCP_REG_UDN_ACCESS:
3461 gen_sigill_reg(env);
3462 break;
3463 default:
3464 fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
3465 g_assert_not_reached();
3466 }
3467 process_pending_signals(env);
3468 }
3469}
3470
3471#endif
3472
3415THREAD CPUState *thread_cpu;
3416
3417void task_settid(TaskState *ts)
3418{
3419 if (ts->ts_tid == 0) {
3420 ts->ts_tid = (pid_t)syscall(SYS_gettid);
3421 }
3422}

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4372 {
4373 int i;
4374 for (i = 0; i < 16; i++) {
4375 env->regs[i] = regs->gprs[i];
4376 }
4377 env->psw.mask = regs->psw.mask;
4378 env->psw.addr = regs->psw.addr;
4379 }
3473THREAD CPUState *thread_cpu;
3474
3475void task_settid(TaskState *ts)
3476{
3477 if (ts->ts_tid == 0) {
3478 ts->ts_tid = (pid_t)syscall(SYS_gettid);
3479 }
3480}

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4430 {
4431 int i;
4432 for (i = 0; i < 16; i++) {
4433 env->regs[i] = regs->gprs[i];
4434 }
4435 env->psw.mask = regs->psw.mask;
4436 env->psw.addr = regs->psw.addr;
4437 }
4438#elif defined(TARGET_TILEGX)
4439 {
4440 int i;
4441 for (i = 0; i < TILEGX_R_COUNT; i++) {
4442 env->regs[i] = regs->regs[i];
4443 }
4444 for (i = 0; i < TILEGX_SPR_COUNT; i++) {
4445 env->spregs[i] = 0;
4446 }
4447 env->pc = regs->pc;
4448 }
4380#else
4381#error unsupported target CPU
4382#endif
4383
4384#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
4385 ts->stack_base = info->start_stack;
4386 ts->heap_base = info->brk;
4387 /* This will be filled in on the first SYS_HEAPINFO call. */

--- 15 unchanged lines hidden --- 		4449#else
4450#error unsupported target CPU
4451#endif
4452
4453#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
4454 ts->stack_base = info->start_stack;
4455 ts->heap_base = info->brk;
4456 /* This will be filled in on the first SYS_HEAPINFO call. */

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