virt.h (d9bbfea646e86426d549bd612cd9f91e49aa50c2) virt.h (2a8756ed7d64f8fed6ad50fb062f7118e47c856c)
1/*
2 * SiFive VirtIO Board
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.

--- 41 unchanged lines hidden (view full) ---

50
51enum {
52 UART0_IRQ = 10,
53 VIRTIO_IRQ = 1, /* 1 to 8 */
54 VIRTIO_COUNT = 8,
55 VIRTIO_NDEV = 10
56};
57
1/*
2 * SiFive VirtIO Board
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.

--- 41 unchanged lines hidden (view full) ---

50
51enum {
52 UART0_IRQ = 10,
53 VIRTIO_IRQ = 1, /* 1 to 8 */
54 VIRTIO_COUNT = 8,
55 VIRTIO_NDEV = 10
56};
57
58enum {
59 VIRT_CLOCK_FREQ = 1000000000
60};
61
58#define VIRT_PLIC_HART_CONFIG "MS"
59#define VIRT_PLIC_NUM_SOURCES 127
60#define VIRT_PLIC_NUM_PRIORITIES 7
61#define VIRT_PLIC_PRIORITY_BASE 0x0
62#define VIRT_PLIC_PENDING_BASE 0x1000
63#define VIRT_PLIC_ENABLE_BASE 0x2000
64#define VIRT_PLIC_ENABLE_STRIDE 0x80
65#define VIRT_PLIC_CONTEXT_BASE 0x200000
66#define VIRT_PLIC_CONTEXT_STRIDE 0x1000
67
68#if defined(TARGET_RISCV32)
69#define VIRT_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
70#elif defined(TARGET_RISCV64)
71#define VIRT_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0
72#endif
73
74#endif
62#define VIRT_PLIC_HART_CONFIG "MS"
63#define VIRT_PLIC_NUM_SOURCES 127
64#define VIRT_PLIC_NUM_PRIORITIES 7
65#define VIRT_PLIC_PRIORITY_BASE 0x0
66#define VIRT_PLIC_PENDING_BASE 0x1000
67#define VIRT_PLIC_ENABLE_BASE 0x2000
68#define VIRT_PLIC_ENABLE_STRIDE 0x80
69#define VIRT_PLIC_CONTEXT_BASE 0x200000
70#define VIRT_PLIC_CONTEXT_STRIDE 0x1000
71
72#if defined(TARGET_RISCV32)
73#define VIRT_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
74#elif defined(TARGET_RISCV64)
75#define VIRT_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0
76#endif
77
78#endif