spike.h (d9bbfea646e86426d549bd612cd9f91e49aa50c2) spike.h (2a8756ed7d64f8fed6ad50fb062f7118e47c856c)
1/*
2 * Spike machine interface
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.

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37
38
39enum {
40 SPIKE_MROM,
41 SPIKE_CLINT,
42 SPIKE_DRAM
43};
44
1/*
2 * Spike machine interface
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.

--- 28 unchanged lines hidden (view full) ---

37
38
39enum {
40 SPIKE_MROM,
41 SPIKE_CLINT,
42 SPIKE_DRAM
43};
44
45enum {
46 SPIKE_CLOCK_FREQ = 1000000000
47};
48
45#if defined(TARGET_RISCV32)
46#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1
47#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
48#elif defined(TARGET_RISCV64)
49#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV64GCSU_V1_09_1
50#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0
51#endif
52
53#endif
49#if defined(TARGET_RISCV32)
50#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1
51#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
52#elif defined(TARGET_RISCV64)
53#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV64GCSU_V1_09_1
54#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0
55#endif
56
57#endif