xlnx-zynqmp.h (fc04a730b7e60f4a62d6260d4eb9c537d1d3643f) xlnx-zynqmp.h (52c16b458ab2f8766867bc5fc099b0a604a36f77)
1/*
2 * Xilinx Zynq MPSoC emulation
3 *
4 * Copyright (C) 2015 Xilinx Inc
5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the

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41#define XLNX_ZYNQMP_GIC_REGIONS 2
42
43/* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
44 * and under-decodes the 64k region. This mirrors the 4k regions to every 4k
45 * aligned address in the 64k region. To implement each GIC region needs a
46 * number of memory region aliases.
47 */
48
1/*
2 * Xilinx Zynq MPSoC emulation
3 *
4 * Copyright (C) 2015 Xilinx Inc
5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the

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41#define XLNX_ZYNQMP_GIC_REGIONS 2
42
43/* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
44 * and under-decodes the 64k region. This mirrors the 4k regions to every 4k
45 * aligned address in the 64k region. To implement each GIC region needs a
46 * number of memory region aliases.
47 */
48
49#define XLNX_ZYNQMP_GIC_REGION_SIZE 0x4000
49#define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000
50#define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE - 1)
51
52typedef struct XlnxZynqMPState {
53 /*< private >*/
54 DeviceState parent_obj;
55
56 /*< public >*/
57 ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS];

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50#define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE - 1)
51
52typedef struct XlnxZynqMPState {
53 /*< private >*/
54 DeviceState parent_obj;
55
56 /*< public >*/
57 ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS];

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