npcm7xx.h (6f8a81fc296535f73c48cf9563862e088cc71c57) npcm7xx.h (0a9df6cb9fb8f98258e51797e59ecaf9ef6b79a2)
1/*
2 * Nuvoton NPCM7xx SoC family.
3 *
4 * Copyright 2020 Google LLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or

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30#include "hw/misc/npcm7xx_rng.h"
31#include "hw/net/npcm7xx_emc.h"
32#include "hw/nvram/npcm7xx_otp.h"
33#include "hw/timer/npcm7xx_timer.h"
34#include "hw/ssi/npcm7xx_fiu.h"
35#include "hw/usb/hcd-ehci.h"
36#include "hw/usb/hcd-ohci.h"
37#include "target/arm/cpu.h"
1/*
2 * Nuvoton NPCM7xx SoC family.
3 *
4 * Copyright 2020 Google LLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or

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30#include "hw/misc/npcm7xx_rng.h"
31#include "hw/net/npcm7xx_emc.h"
32#include "hw/nvram/npcm7xx_otp.h"
33#include "hw/timer/npcm7xx_timer.h"
34#include "hw/ssi/npcm7xx_fiu.h"
35#include "hw/usb/hcd-ehci.h"
36#include "hw/usb/hcd-ohci.h"
37#include "target/arm/cpu.h"
38#include "hw/sd/npcm7xx_sdhci.h"
38
39#define NPCM7XX_MAX_NUM_CPUS (2)
40
41/* The first half of the address space is reserved for DDR4 DRAM. */
42#define NPCM7XX_DRAM_BA (0x00000000)
43#define NPCM7XX_DRAM_SZ (2 * GiB)
44
45/* Magic addresses for setting up direct kernel booting and SMP boot stubs. */

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98 NPCM7xxMCState mc;
99 NPCM7xxRNGState rng;
100 NPCM7xxGPIOState gpio[8];
101 NPCM7xxSMBusState smbus[16];
102 EHCISysBusState ehci;
103 OHCISysBusState ohci;
104 NPCM7xxFIUState fiu[2];
105 NPCM7xxEMCState emc[2];
39
40#define NPCM7XX_MAX_NUM_CPUS (2)
41
42/* The first half of the address space is reserved for DDR4 DRAM. */
43#define NPCM7XX_DRAM_BA (0x00000000)
44#define NPCM7XX_DRAM_SZ (2 * GiB)
45
46/* Magic addresses for setting up direct kernel booting and SMP boot stubs. */

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99 NPCM7xxMCState mc;
100 NPCM7xxRNGState rng;
101 NPCM7xxGPIOState gpio[8];
102 NPCM7xxSMBusState smbus[16];
103 EHCISysBusState ehci;
104 OHCISysBusState ohci;
105 NPCM7xxFIUState fiu[2];
106 NPCM7xxEMCState emc[2];
107 NPCM7xxSDHCIState mmc;
106} NPCM7xxState;
107
108#define TYPE_NPCM7XX "npcm7xx"
109#define NPCM7XX(obj) OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX)
110
111#define TYPE_NPCM730 "npcm730"
112#define TYPE_NPCM750 "npcm750"
113

--- 26 unchanged lines hidden --- 		108} NPCM7xxState;
109
110#define TYPE_NPCM7XX "npcm7xx"
111#define NPCM7XX(obj) OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX)
112
113#define TYPE_NPCM730 "npcm730"
114#define TYPE_NPCM750 "npcm750"
115

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