npcm7xx.h (2d2c73d0e3d504a61f868e46e6abd5643f38091b) | npcm7xx.h (326ccfe240ca9ef4f659a241b39390fa956e999b) |
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1/* 2 * Nuvoton NPCM7xx SoC family. 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or --- 7 unchanged lines hidden (view full) --- 16#ifndef NPCM7XX_H 17#define NPCM7XX_H 18 19#include "hw/boards.h" 20#include "hw/cpu/a9mpcore.h" 21#include "hw/mem/npcm7xx_mc.h" 22#include "hw/misc/npcm7xx_clk.h" 23#include "hw/misc/npcm7xx_gcr.h" | 1/* 2 * Nuvoton NPCM7xx SoC family. 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or --- 7 unchanged lines hidden (view full) --- 16#ifndef NPCM7XX_H 17#define NPCM7XX_H 18 19#include "hw/boards.h" 20#include "hw/cpu/a9mpcore.h" 21#include "hw/mem/npcm7xx_mc.h" 22#include "hw/misc/npcm7xx_clk.h" 23#include "hw/misc/npcm7xx_gcr.h" |
24#include "hw/misc/npcm7xx_rng.h" |
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24#include "hw/nvram/npcm7xx_otp.h" 25#include "hw/timer/npcm7xx_timer.h" 26#include "hw/ssi/npcm7xx_fiu.h" 27#include "target/arm/cpu.h" 28 29#define NPCM7XX_MAX_NUM_CPUS (2) 30 31/* The first half of the address space is reserved for DDR4 DRAM. */ --- 38 unchanged lines hidden (view full) --- 70 MemoryRegion *dram; 71 72 NPCM7xxGCRState gcr; 73 NPCM7xxCLKState clk; 74 NPCM7xxTimerCtrlState tim[3]; 75 NPCM7xxOTPState key_storage; 76 NPCM7xxOTPState fuse_array; 77 NPCM7xxMCState mc; | 25#include "hw/nvram/npcm7xx_otp.h" 26#include "hw/timer/npcm7xx_timer.h" 27#include "hw/ssi/npcm7xx_fiu.h" 28#include "target/arm/cpu.h" 29 30#define NPCM7XX_MAX_NUM_CPUS (2) 31 32/* The first half of the address space is reserved for DDR4 DRAM. */ --- 38 unchanged lines hidden (view full) --- 71 MemoryRegion *dram; 72 73 NPCM7xxGCRState gcr; 74 NPCM7xxCLKState clk; 75 NPCM7xxTimerCtrlState tim[3]; 76 NPCM7xxOTPState key_storage; 77 NPCM7xxOTPState fuse_array; 78 NPCM7xxMCState mc; |
79 NPCM7xxRNGState rng; |
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78 NPCM7xxFIUState fiu[2]; 79} NPCM7xxState; 80 81#define TYPE_NPCM7XX "npcm7xx" 82#define NPCM7XX(obj) OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX) 83 84#define TYPE_NPCM730 "npcm730" 85#define TYPE_NPCM750 "npcm750" --- 27 unchanged lines hidden --- | 80 NPCM7xxFIUState fiu[2]; 81} NPCM7xxState; 82 83#define TYPE_NPCM7XX "npcm7xx" 84#define NPCM7XX(obj) OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX) 85 86#define TYPE_NPCM730 "npcm730" 87#define TYPE_NPCM750 "npcm750" --- 27 unchanged lines hidden --- |