npcm7xx.h (1351f892467bd8d9655b43b8fbf10a8d08890612) | npcm7xx.h (b821242c7b3b174bbf7c01a19c93c4e52fedab5d) |
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1/* 2 * Nuvoton NPCM7xx SoC family. 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or --- 9 unchanged lines hidden (view full) --- 18 19#include "hw/boards.h" 20#include "hw/cpu/a9mpcore.h" 21#include "hw/mem/npcm7xx_mc.h" 22#include "hw/misc/npcm7xx_clk.h" 23#include "hw/misc/npcm7xx_gcr.h" 24#include "hw/nvram/npcm7xx_otp.h" 25#include "hw/timer/npcm7xx_timer.h" | 1/* 2 * Nuvoton NPCM7xx SoC family. 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or --- 9 unchanged lines hidden (view full) --- 18 19#include "hw/boards.h" 20#include "hw/cpu/a9mpcore.h" 21#include "hw/mem/npcm7xx_mc.h" 22#include "hw/misc/npcm7xx_clk.h" 23#include "hw/misc/npcm7xx_gcr.h" 24#include "hw/nvram/npcm7xx_otp.h" 25#include "hw/timer/npcm7xx_timer.h" |
26#include "hw/ssi/npcm7xx_fiu.h" |
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26#include "target/arm/cpu.h" 27 28#define NPCM7XX_MAX_NUM_CPUS (2) 29 30/* The first half of the address space is reserved for DDR4 DRAM. */ 31#define NPCM7XX_DRAM_BA (0x00000000) 32#define NPCM7XX_DRAM_SZ (2 * GiB) 33 --- 34 unchanged lines hidden (view full) --- 68 MemoryRegion *dram; 69 70 NPCM7xxGCRState gcr; 71 NPCM7xxCLKState clk; 72 NPCM7xxTimerCtrlState tim[3]; 73 NPCM7xxOTPState key_storage; 74 NPCM7xxOTPState fuse_array; 75 NPCM7xxMCState mc; | 27#include "target/arm/cpu.h" 28 29#define NPCM7XX_MAX_NUM_CPUS (2) 30 31/* The first half of the address space is reserved for DDR4 DRAM. */ 32#define NPCM7XX_DRAM_BA (0x00000000) 33#define NPCM7XX_DRAM_SZ (2 * GiB) 34 --- 34 unchanged lines hidden (view full) --- 69 MemoryRegion *dram; 70 71 NPCM7xxGCRState gcr; 72 NPCM7xxCLKState clk; 73 NPCM7xxTimerCtrlState tim[3]; 74 NPCM7xxOTPState key_storage; 75 NPCM7xxOTPState fuse_array; 76 NPCM7xxMCState mc; |
77 NPCM7xxFIUState fiu[2]; |
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76} NPCM7xxState; 77 78#define TYPE_NPCM7XX "npcm7xx" 79#define NPCM7XX(obj) OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX) 80 81#define TYPE_NPCM730 "npcm730" 82#define TYPE_NPCM750 "npcm750" 83 --- 26 unchanged lines hidden --- | 78} NPCM7xxState; 79 80#define TYPE_NPCM7XX "npcm7xx" 81#define NPCM7XX(obj) OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX) 82 83#define TYPE_NPCM730 "npcm730" 84#define TYPE_NPCM750 "npcm750" 85 --- 26 unchanged lines hidden --- |