exec-all.h (600b819f235d6b6eb33fc33e09fe64f53eb9a9a6) exec-all.h (c13b27d826797ee12dcf4e4c289a7a6c401e620b)
1/*
2 * internal execution defines for qemu
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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276void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr,
277 target_ulong len, uint16_t idxmap,
278 unsigned bits);
279
280/* Similarly, with broadcast and syncing. */
281void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
282 target_ulong len, uint16_t idxmap,
283 unsigned bits);
1/*
2 * internal execution defines for qemu
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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276void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr,
277 target_ulong len, uint16_t idxmap,
278 unsigned bits);
279
280/* Similarly, with broadcast and syncing. */
281void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
282 target_ulong len, uint16_t idxmap,
283 unsigned bits);
284void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
285 target_ulong addr,
286 target_ulong len,
287 uint16_t idxmap,
288 unsigned bits);
284
285/**
286 * tlb_set_page_with_attrs:
287 * @cpu: CPU to add this TLB entry for
288 * @vaddr: virtual address of page to add entry for
289 * @paddr: physical address of the page
290 * @attrs: memory transaction attributes
291 * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)

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392}
393static inline void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu,
394 target_ulong addr,
395 target_ulong len,
396 uint16_t idxmap,
397 unsigned bits)
398{
399}
289
290/**
291 * tlb_set_page_with_attrs:
292 * @cpu: CPU to add this TLB entry for
293 * @vaddr: virtual address of page to add entry for
294 * @paddr: physical address of the page
295 * @attrs: memory transaction attributes
296 * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)

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397}
398static inline void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu,
399 target_ulong addr,
400 target_ulong len,
401 uint16_t idxmap,
402 unsigned bits)
403{
404}
405static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
406 target_ulong addr,
407 target_long len,
408 uint16_t idxmap,
409 unsigned bits)
410{
411}
400#endif
401/**
402 * probe_access:
403 * @env: CPUArchState
404 * @addr: guest virtual address to look up
405 * @size: size of the access
406 * @access_type: read, write or execute permission
407 * @mmu_idx: MMU index to use for lookup

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413/**
414 * probe_access:
415 * @env: CPUArchState
416 * @addr: guest virtual address to look up
417 * @size: size of the access
418 * @access_type: read, write or execute permission
419 * @mmu_idx: MMU index to use for lookup

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