cpu-defs.h (31e213e30617b986a6e8ab4d9a0646eb4e6a4227) cpu-defs.h (53d284554cfb476a43807fe94fa59909ed5d9ff8)
1/*
2 * common defines for all CPUs
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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136 * + the ram_addr_t of the target RAM (if the physical section
137 * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM)
138 * + the offset within the target MemoryRegion (otherwise)
139 */
140 hwaddr addr;
141 MemTxAttrs attrs;
142} CPUIOTLBEntry;
143
1/*
2 * common defines for all CPUs
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

--- 127 unchanged lines hidden (view full) ---

136 * + the ram_addr_t of the target RAM (if the physical section
137 * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM)
138 * + the offset within the target MemoryRegion (otherwise)
139 */
140 hwaddr addr;
141 MemTxAttrs attrs;
142} CPUIOTLBEntry;
143
144/*
145 * Data elements that are shared between all MMU modes.
146 */
147typedef struct CPUTLBCommon {
148 /* lock serializes updates to tlb_table and tlb_v_table */
149 QemuSpin lock;
150} CPUTLBCommon;
151
152/*
153 * The meaning of each of the MMU modes is defined in the target code.
154 * Note that NB_MMU_MODES is not yet defined; we can only reference it
155 * within preprocessor defines that will be expanded later.
156 */
144#define CPU_COMMON_TLB \
157#define CPU_COMMON_TLB \
145 /* The meaning of the MMU modes is defined in the target code. */ \
146 /* tlb_lock serializes updates to tlb_table and tlb_v_table */ \
147 QemuSpin tlb_lock; \
158 CPUTLBCommon tlb_c; \
148 CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
149 CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \
150 CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
151 CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; \
152 size_t tlb_flush_count; \
153 target_ulong tlb_flush_addr; \
154 target_ulong tlb_flush_mask; \
155 target_ulong vtlb_index; \

--- 13 unchanged lines hidden --- 		159 CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
160 CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \
161 CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
162 CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; \
163 size_t tlb_flush_count; \
164 target_ulong tlb_flush_addr; \
165 target_ulong tlb_flush_mask; \
166 target_ulong vtlb_index; \

--- 13 unchanged lines hidden ---