cpu-common.h (98c710f2d5cdf37f29a267352eb1f3c28cbf369d) cpu-common.h (2cd53943115be5118b5b2d4b80ee0a39c94c4f73)
1#ifndef CPU_COMMON_H
1#ifndef CPU_COMMON_H
2#define CPU_COMMON_H 1
2#define CPU_COMMON_H
3
4/* CPU interfaces that are target independent. */
5
6#ifndef CONFIG_USER_ONLY
7#include "exec/hwaddr.h"
8#endif
9
10#include "qemu/bswap.h"

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18 *
19 * State commonly used for iterating over CPU models.
20 */
21typedef struct CPUListState {
22 fprintf_function cpu_fprintf;
23 FILE *file;
24} CPUListState;
25
3
4/* CPU interfaces that are target independent. */
5
6#ifndef CONFIG_USER_ONLY
7#include "exec/hwaddr.h"
8#endif
9
10#include "qemu/bswap.h"

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18 *
19 * State commonly used for iterating over CPU models.
20 */
21typedef struct CPUListState {
22 fprintf_function cpu_fprintf;
23 FILE *file;
24} CPUListState;
25
26typedef enum MMUAccessType {
27 MMU_DATA_LOAD = 0,
28 MMU_DATA_STORE = 1,
29 MMU_INST_FETCH = 2
30} MMUAccessType;
26/* The CPU list lock nests outside tb_lock/tb_unlock. */
27void qemu_init_cpu_list(void);
28void cpu_list_lock(void);
29void cpu_list_unlock(void);
31
30
31void tcg_flush_softmmu_tlb(CPUState *cs);
32
32#if !defined(CONFIG_USER_ONLY)
33
34enum device_endian {
35 DEVICE_NATIVE_ENDIAN,
36 DEVICE_BIG_ENDIAN,
37 DEVICE_LITTLE_ENDIAN,
38};
39
33#if !defined(CONFIG_USER_ONLY)
34
35enum device_endian {
36 DEVICE_NATIVE_ENDIAN,
37 DEVICE_BIG_ENDIAN,
38 DEVICE_LITTLE_ENDIAN,
39};
40
41#if defined(HOST_WORDS_BIGENDIAN)
42#define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN
43#else
44#define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN
45#endif
46
40/* address in the RAM (different from a physical address) */
41#if defined(CONFIG_XEN_BACKEND)
42typedef uint64_t ram_addr_t;
43# define RAM_ADDR_MAX UINT64_MAX
44# define RAM_ADDR_FMT "%" PRIx64
45#else
46typedef uintptr_t ram_addr_t;
47# define RAM_ADDR_MAX UINTPTR_MAX

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59/* This should not be used by devices. */
60ram_addr_t qemu_ram_addr_from_host(void *ptr);
61RAMBlock *qemu_ram_block_by_name(const char *name);
62RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
63 ram_addr_t *offset);
64void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev);
65void qemu_ram_unset_idstr(RAMBlock *block);
66const char *qemu_ram_get_idstr(RAMBlock *rb);
47/* address in the RAM (different from a physical address) */
48#if defined(CONFIG_XEN_BACKEND)
49typedef uint64_t ram_addr_t;
50# define RAM_ADDR_MAX UINT64_MAX
51# define RAM_ADDR_FMT "%" PRIx64
52#else
53typedef uintptr_t ram_addr_t;
54# define RAM_ADDR_MAX UINTPTR_MAX

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66/* This should not be used by devices. */
67ram_addr_t qemu_ram_addr_from_host(void *ptr);
68RAMBlock *qemu_ram_block_by_name(const char *name);
69RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
70 ram_addr_t *offset);
71void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev);
72void qemu_ram_unset_idstr(RAMBlock *block);
73const char *qemu_ram_get_idstr(RAMBlock *rb);
74bool qemu_ram_is_shared(RAMBlock *rb);
75size_t qemu_ram_pagesize(RAMBlock *block);
76size_t qemu_ram_pagesize_largest(void);
67
68void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
69 int len, int is_write);
70static inline void cpu_physical_memory_read(hwaddr addr,
71 void *buf, int len)
72{
73 cpu_physical_memory_rw(addr, buf, len, 0);
74}

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89
90/* Coalesced MMIO regions are areas where write operations can be reordered.
91 * This usually implies that write operations are side-effect free. This allows
92 * batching which can make a major impact on performance when using
93 * virtualization.
94 */
95void qemu_flush_coalesced_mmio_buffer(void);
96
77
78void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
79 int len, int is_write);
80static inline void cpu_physical_memory_read(hwaddr addr,
81 void *buf, int len)
82{
83 cpu_physical_memory_rw(addr, buf, len, 0);
84}

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99
100/* Coalesced MMIO regions are areas where write operations can be reordered.
101 * This usually implies that write operations are side-effect free. This allows
102 * batching which can make a major impact on performance when using
103 * virtualization.
104 */
105void qemu_flush_coalesced_mmio_buffer(void);
106
97uint32_t ldub_phys(AddressSpace *as, hwaddr addr);
98uint32_t lduw_le_phys(AddressSpace *as, hwaddr addr);
99uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr);
100uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr);
101uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr);
102uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr);
103uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr);
104void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val);
105void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val);
106void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val);
107void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val);
108void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val);
109void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val);
110void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val);
111
112void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
113 const uint8_t *buf, int len);
114void cpu_flush_icache_range(hwaddr start, int len);
115
116extern struct MemoryRegion io_mem_rom;
117extern struct MemoryRegion io_mem_notdirty;
118
119typedef int (RAMBlockIterFunc)(const char *block_name, void *host_addr,
120 ram_addr_t offset, ram_addr_t length, void *opaque);
121
122int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque);
107void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
108 const uint8_t *buf, int len);
109void cpu_flush_icache_range(hwaddr start, int len);
110
111extern struct MemoryRegion io_mem_rom;
112extern struct MemoryRegion io_mem_notdirty;
113
114typedef int (RAMBlockIterFunc)(const char *block_name, void *host_addr,
115 ram_addr_t offset, ram_addr_t length, void *opaque);
116
117int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque);
118int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length);
123
124#endif
125
119
120#endif
121
126#endif /* !CPU_COMMON_H */
122#endif /* CPU_COMMON_H */