nvme.h (0ebf76aae58324b8f7bf6af798696687f5f4c2a9) nvme.h (771dbc3ac484af35cddf7e4971e66a1fd1a07156)
1#ifndef BLOCK_NVME_H
2#define BLOCK_NVME_H
3
4typedef struct QEMU_PACKED NvmeBar {
5 uint64_t cap;
6 uint32_t vs;
7 uint32_t intms;
8 uint32_t intmc;

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53 NVME_REG_PMRCTL = offsetof(NvmeBar, pmrctl),
54 NVME_REG_PMRSTS = offsetof(NvmeBar, pmrsts),
55 NVME_REG_PMREBS = offsetof(NvmeBar, pmrebs),
56 NVME_REG_PMRSWTP = offsetof(NvmeBar, pmrswtp),
57 NVME_REG_PMRMSCL = offsetof(NvmeBar, pmrmscl),
58 NVME_REG_PMRMSCU = offsetof(NvmeBar, pmrmscu),
59};
60
1#ifndef BLOCK_NVME_H
2#define BLOCK_NVME_H
3
4typedef struct QEMU_PACKED NvmeBar {
5 uint64_t cap;
6 uint32_t vs;
7 uint32_t intms;
8 uint32_t intmc;

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53 NVME_REG_PMRCTL = offsetof(NvmeBar, pmrctl),
54 NVME_REG_PMRSTS = offsetof(NvmeBar, pmrsts),
55 NVME_REG_PMREBS = offsetof(NvmeBar, pmrebs),
56 NVME_REG_PMRSWTP = offsetof(NvmeBar, pmrswtp),
57 NVME_REG_PMRMSCL = offsetof(NvmeBar, pmrmscl),
58 NVME_REG_PMRMSCU = offsetof(NvmeBar, pmrmscu),
59};
60
61typedef struct QEMU_PACKED NvmeEndGrpLog {
62 uint8_t critical_warning;
63 uint8_t rsvd[2];
64 uint8_t avail_spare;
65 uint8_t avail_spare_thres;
66 uint8_t percet_used;
67 uint8_t rsvd1[26];
68 uint64_t end_estimate[2];
69 uint64_t data_units_read[2];
70 uint64_t data_units_written[2];
71 uint64_t media_units_written[2];
72 uint64_t host_read_commands[2];
73 uint64_t host_write_commands[2];
74 uint64_t media_integrity_errors[2];
75 uint64_t no_err_info_log_entries[2];
76 uint8_t rsvd2[352];
77} NvmeEndGrpLog;
78
61enum NvmeCapShift {
62 CAP_MQES_SHIFT = 0,
63 CAP_CQR_SHIFT = 16,
64 CAP_AMS_SHIFT = 17,
65 CAP_TO_SHIFT = 24,
66 CAP_DSTRD_SHIFT = 32,
67 CAP_NSSRS_SHIFT = 36,
68 CAP_CSS_SHIFT = 37,

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1000 NVME_CMD_EFF_NCC = 1 << 2,
1001 NVME_CMD_EFF_NIC = 1 << 3,
1002 NVME_CMD_EFF_CCC = 1 << 4,
1003 NVME_CMD_EFF_CSE_MASK = 3 << 16,
1004 NVME_CMD_EFF_UUID_SEL = 1 << 19,
1005};
1006
1007enum NvmeLogIdentifier {
79enum NvmeCapShift {
80 CAP_MQES_SHIFT = 0,
81 CAP_CQR_SHIFT = 16,
82 CAP_AMS_SHIFT = 17,
83 CAP_TO_SHIFT = 24,
84 CAP_DSTRD_SHIFT = 32,
85 CAP_NSSRS_SHIFT = 36,
86 CAP_CSS_SHIFT = 37,

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1018 NVME_CMD_EFF_NCC = 1 << 2,
1019 NVME_CMD_EFF_NIC = 1 << 3,
1020 NVME_CMD_EFF_CCC = 1 << 4,
1021 NVME_CMD_EFF_CSE_MASK = 3 << 16,
1022 NVME_CMD_EFF_UUID_SEL = 1 << 19,
1023};
1024
1025enum NvmeLogIdentifier {
1008 NVME_LOG_ERROR_INFO = 0x01,
1009 NVME_LOG_SMART_INFO = 0x02,
1010 NVME_LOG_FW_SLOT_INFO = 0x03,
1011 NVME_LOG_CHANGED_NSLIST = 0x04,
1012 NVME_LOG_CMD_EFFECTS = 0x05,
1026 NVME_LOG_ERROR_INFO = 0x01,
1027 NVME_LOG_SMART_INFO = 0x02,
1028 NVME_LOG_FW_SLOT_INFO = 0x03,
1029 NVME_LOG_CHANGED_NSLIST = 0x04,
1030 NVME_LOG_CMD_EFFECTS = 0x05,
1031 NVME_LOG_ENDGRP = 0x09,
1013};
1014
1015typedef struct QEMU_PACKED NvmePSD {
1016 uint16_t mp;
1017 uint16_t reserved;
1018 uint32_t enlat;
1019 uint32_t exlat;
1020 uint8_t rrt;

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1086 uint16_t edstt;
1087 uint8_t dsto;
1088 uint8_t fwug;
1089 uint16_t kas;
1090 uint16_t hctma;
1091 uint16_t mntmt;
1092 uint16_t mxtmt;
1093 uint32_t sanicap;
1032};
1033
1034typedef struct QEMU_PACKED NvmePSD {
1035 uint16_t mp;
1036 uint16_t reserved;
1037 uint32_t enlat;
1038 uint32_t exlat;
1039 uint8_t rrt;

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1105 uint16_t edstt;
1106 uint8_t dsto;
1107 uint8_t fwug;
1108 uint16_t kas;
1109 uint16_t hctma;
1110 uint16_t mntmt;
1111 uint16_t mxtmt;
1112 uint32_t sanicap;
1094 uint8_t rsvd332[180];
1113 uint8_t rsvd332[6];
1114 uint16_t nsetidmax;
1115 uint16_t endgidmax;
1116 uint8_t rsvd342[170];
1095 uint8_t sqes;
1096 uint8_t cqes;
1097 uint16_t maxcmd;
1098 uint32_t nn;
1099 uint16_t oncs;
1100 uint16_t fuses;
1101 uint8_t fna;
1102 uint8_t vwc;

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1129 uint8_t rsvd16[4080];
1130} NvmeIdCtrlNvm;
1131
1132enum NvmeIdCtrlOaes {
1133 NVME_OAES_NS_ATTR = 1 << 8,
1134};
1135
1136enum NvmeIdCtrlCtratt {
1117 uint8_t sqes;
1118 uint8_t cqes;
1119 uint16_t maxcmd;
1120 uint32_t nn;
1121 uint16_t oncs;
1122 uint16_t fuses;
1123 uint8_t fna;
1124 uint8_t vwc;

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1151 uint8_t rsvd16[4080];
1152} NvmeIdCtrlNvm;
1153
1154enum NvmeIdCtrlOaes {
1155 NVME_OAES_NS_ATTR = 1 << 8,
1156};
1157
1158enum NvmeIdCtrlCtratt {
1159 NVME_CTRATT_ENDGRPS = 1 << 4,
1137 NVME_CTRATT_ELBAS = 1 << 15,
1138};
1139
1140enum NvmeIdCtrlOacs {
1141 NVME_OACS_SECURITY = 1 << 0,
1142 NVME_OACS_FORMAT = 1 << 1,
1143 NVME_OACS_FW = 1 << 2,
1144 NVME_OACS_NS_MGMT = 1 << 3,

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1222#define NVME_TEMP_TMPSEL(temp) ((temp >> 16) & 0xf)
1223#define NVME_TEMP_TMPSEL_COMPOSITE 0x0
1224
1225#define NVME_TEMP_TMPTH(temp) (temp & 0xffff)
1226
1227#define NVME_AEC_SMART(aec) (aec & 0xff)
1228#define NVME_AEC_NS_ATTR(aec) ((aec >> 8) & 0x1)
1229#define NVME_AEC_FW_ACTIVATION(aec) ((aec >> 9) & 0x1)
1160 NVME_CTRATT_ELBAS = 1 << 15,
1161};
1162
1163enum NvmeIdCtrlOacs {
1164 NVME_OACS_SECURITY = 1 << 0,
1165 NVME_OACS_FORMAT = 1 << 1,
1166 NVME_OACS_FW = 1 << 2,
1167 NVME_OACS_NS_MGMT = 1 << 3,

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1245#define NVME_TEMP_TMPSEL(temp) ((temp >> 16) & 0xf)
1246#define NVME_TEMP_TMPSEL_COMPOSITE 0x0
1247
1248#define NVME_TEMP_TMPTH(temp) (temp & 0xffff)
1249
1250#define NVME_AEC_SMART(aec) (aec & 0xff)
1251#define NVME_AEC_NS_ATTR(aec) ((aec >> 8) & 0x1)
1252#define NVME_AEC_FW_ACTIVATION(aec) ((aec >> 9) & 0x1)
1253#define NVME_AEC_ENDGRP_NOTICE(aec) ((aec >> 14) & 0x1)
1230
1231#define NVME_ERR_REC_TLER(err_rec) (err_rec & 0xffff)
1232#define NVME_ERR_REC_DULBE(err_rec) (err_rec & 0x10000)
1233
1234enum NvmeFeatureIds {
1235 NVME_ARBITRATION = 0x1,
1236 NVME_POWER_MANAGEMENT = 0x2,
1237 NVME_LBA_RANGE_TYPE = 0x3,

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1333 uint16_t npwg;
1334 uint16_t npwa;
1335 uint16_t npdg;
1336 uint16_t npda;
1337 uint16_t nows;
1338 uint16_t mssrl;
1339 uint32_t mcl;
1340 uint8_t msrc;
1254
1255#define NVME_ERR_REC_TLER(err_rec) (err_rec & 0xffff)
1256#define NVME_ERR_REC_DULBE(err_rec) (err_rec & 0x10000)
1257
1258enum NvmeFeatureIds {
1259 NVME_ARBITRATION = 0x1,
1260 NVME_POWER_MANAGEMENT = 0x2,
1261 NVME_LBA_RANGE_TYPE = 0x3,

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1357 uint16_t npwg;
1358 uint16_t npwa;
1359 uint16_t npdg;
1360 uint16_t npda;
1361 uint16_t nows;
1362 uint16_t mssrl;
1363 uint32_t mcl;
1364 uint8_t msrc;
1341 uint8_t rsvd81[23];
1365 uint8_t rsvd81[18];
1366 uint8_t nsattr;
1367 uint16_t nvmsetid;
1368 uint16_t endgid;
1342 uint8_t nguid[16];
1343 uint64_t eui64;
1344 NvmeLBAF lbaf[NVME_MAX_NLBAF];
1345 uint8_t vs[3712];
1346} NvmeIdNs;
1347
1348#define NVME_ID_NS_NVM_ELBAF_PIF(elbaf) (((elbaf) >> 7) & 0x3)
1349

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1650 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsZoned) != 4096);
1651 QEMU_BUILD_BUG_ON(sizeof(NvmeSglDescriptor) != 16);
1652 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsDescr) != 4);
1653 QEMU_BUILD_BUG_ON(sizeof(NvmeZoneDescr) != 64);
1654 QEMU_BUILD_BUG_ON(sizeof(NvmeDifTuple) != 16);
1655 QEMU_BUILD_BUG_ON(sizeof(NvmePriCtrlCap) != 4096);
1656 QEMU_BUILD_BUG_ON(sizeof(NvmeSecCtrlEntry) != 32);
1657 QEMU_BUILD_BUG_ON(sizeof(NvmeSecCtrlList) != 4096);
1369 uint8_t nguid[16];
1370 uint64_t eui64;
1371 NvmeLBAF lbaf[NVME_MAX_NLBAF];
1372 uint8_t vs[3712];
1373} NvmeIdNs;
1374
1375#define NVME_ID_NS_NVM_ELBAF_PIF(elbaf) (((elbaf) >> 7) & 0x3)
1376

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1677 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsZoned) != 4096);
1678 QEMU_BUILD_BUG_ON(sizeof(NvmeSglDescriptor) != 16);
1679 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsDescr) != 4);
1680 QEMU_BUILD_BUG_ON(sizeof(NvmeZoneDescr) != 64);
1681 QEMU_BUILD_BUG_ON(sizeof(NvmeDifTuple) != 16);
1682 QEMU_BUILD_BUG_ON(sizeof(NvmePriCtrlCap) != 4096);
1683 QEMU_BUILD_BUG_ON(sizeof(NvmeSecCtrlEntry) != 32);
1684 QEMU_BUILD_BUG_ON(sizeof(NvmeSecCtrlList) != 4096);
1685 QEMU_BUILD_BUG_ON(sizeof(NvmeEndGrpLog) != 512);
1658}
1659#endif
1686}
1687#endif