hcd-uhci.c (501a7ce7270955be151c442c27620fa7af2f3ce5) hcd-uhci.c (719c130dcaa3b1269beed71ca9cf6c43a0219b30)
1/*
2 * USB UHCI controller emulation
3 *
4 * Copyright (c) 2005 Fabrice Bellard
5 *
6 * Copyright (c) 2008 Max Krasnyansky
7 * Magor rewrite of the UHCI data structures parser and frame processor
8 * Support for fully async operation and multiple outstanding transactions

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1186 trace_usb_uhci_schedule_stop();
1187 qemu_del_timer(s->frame_timer);
1188 uhci_async_cancel_all(s);
1189 /* set hchalted bit in status - UHCI11D 2.1.2 */
1190 s->status |= UHCI_STS_HCHALTED;
1191 return;
1192 }
1193
1/*
2 * USB UHCI controller emulation
3 *
4 * Copyright (c) 2005 Fabrice Bellard
5 *
6 * Copyright (c) 2008 Max Krasnyansky
7 * Magor rewrite of the UHCI data structures parser and frame processor
8 * Support for fully async operation and multiple outstanding transactions

--- 1177 unchanged lines hidden (view full) ---

1186 trace_usb_uhci_schedule_stop();
1187 qemu_del_timer(s->frame_timer);
1188 uhci_async_cancel_all(s);
1189 /* set hchalted bit in status - UHCI11D 2.1.2 */
1190 s->status |= UHCI_STS_HCHALTED;
1191 return;
1192 }
1193
1194 /* Complete the previous frame */
1195 if (s->pending_int_mask) {
1196 s->status2 |= s->pending_int_mask;
1197 s->status |= UHCI_STS_USBINT;
1198 uhci_update_irq(s);
1199 }
1200 s->pending_int_mask = 0;
1201
1202 /* Start new frame */
1203 s->frnum = (s->frnum + 1) & 0x7ff;
1204
1194 /* Process the current frame */
1205 trace_usb_uhci_frame_start(s->frnum);
1206
1207 uhci_async_validate_begin(s);
1208
1209 uhci_process_frame(s);
1210
1211 uhci_async_validate_end(s);
1212
1195 trace_usb_uhci_frame_start(s->frnum);
1196
1197 uhci_async_validate_begin(s);
1198
1199 uhci_process_frame(s);
1200
1201 uhci_async_validate_end(s);
1202
1203 /* The uhci spec says frnum reflects the frame currently being processed,
1204 * and the guest must look at frnum - 1 on interrupt, so inc frnum now */
1205 s->frnum = (s->frnum + 1) & 0x7ff;
1206
1207 /* Complete the previous frame */
1208 if (s->pending_int_mask) {
1209 s->status2 |= s->pending_int_mask;
1210 s->status |= UHCI_STS_USBINT;
1211 uhci_update_irq(s);
1212 }
1213 s->pending_int_mask = 0;
1214
1213 qemu_mod_timer(s->frame_timer, s->expire_time);
1214}
1215
1216static const MemoryRegionPortio uhci_portio[] = {
1217 { 0, 32, 2, .write = uhci_ioport_writew, },
1218 { 0, 32, 2, .read = uhci_ioport_readw, },
1219 { 0, 32, 4, .write = uhci_ioport_writel, },
1220 { 0, 32, 4, .read = uhci_ioport_readl, },

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1215 qemu_mod_timer(s->frame_timer, s->expire_time);
1216}
1217
1218static const MemoryRegionPortio uhci_portio[] = {
1219 { 0, 32, 2, .write = uhci_ioport_writew, },
1220 { 0, 32, 2, .read = uhci_ioport_readw, },
1221 { 0, 32, 4, .write = uhci_ioport_writel, },
1222 { 0, 32, 4, .read = uhci_ioport_readl, },

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