npcm7xx_timer.c (2ac88848cb03605e2fae6a035650eea461218af2) npcm7xx_timer.c (7d378ed6e3b4a26f4da887fcccc4c6f1db3dcd42)
1/*
2 * Nuvoton NPCM7xx Timer Controller
3 *
4 * Copyright 2020 Google LLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 */
16
17#include "qemu/osdep.h"
18
19#include "hw/irq.h"
1/*
2 * Nuvoton NPCM7xx Timer Controller
3 *
4 * Copyright 2020 Google LLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 */
16
17#include "qemu/osdep.h"
18
19#include "hw/irq.h"
20#include "hw/qdev-properties.h"
20#include "hw/misc/npcm7xx_clk.h"
21#include "hw/timer/npcm7xx_timer.h"
22#include "migration/vmstate.h"
23#include "qemu/bitops.h"
24#include "qemu/error-report.h"
25#include "qemu/log.h"
26#include "qemu/module.h"
27#include "qemu/timer.h"

--- 27 unchanged lines hidden (view full) ---

55#define NPCM7XX_TCSR_IE BIT(29)
56#define NPCM7XX_TCSR_PERIODIC BIT(27)
57#define NPCM7XX_TCSR_CRST BIT(26)
58#define NPCM7XX_TCSR_CACT BIT(25)
59#define NPCM7XX_TCSR_RSVD 0x01ffff00
60#define NPCM7XX_TCSR_PRESCALE_START 0
61#define NPCM7XX_TCSR_PRESCALE_LEN 8
62
21#include "hw/misc/npcm7xx_clk.h"
22#include "hw/timer/npcm7xx_timer.h"
23#include "migration/vmstate.h"
24#include "qemu/bitops.h"
25#include "qemu/error-report.h"
26#include "qemu/log.h"
27#include "qemu/module.h"
28#include "qemu/timer.h"

--- 27 unchanged lines hidden (view full) ---

56#define NPCM7XX_TCSR_IE BIT(29)
57#define NPCM7XX_TCSR_PERIODIC BIT(27)
58#define NPCM7XX_TCSR_CRST BIT(26)
59#define NPCM7XX_TCSR_CACT BIT(25)
60#define NPCM7XX_TCSR_RSVD 0x01ffff00
61#define NPCM7XX_TCSR_PRESCALE_START 0
62#define NPCM7XX_TCSR_PRESCALE_LEN 8
63
64#define NPCM7XX_WTCR_WTCLK(rv) extract32(rv, 10, 2)
65#define NPCM7XX_WTCR_FREEZE_EN BIT(9)
66#define NPCM7XX_WTCR_WTE BIT(7)
67#define NPCM7XX_WTCR_WTIE BIT(6)
68#define NPCM7XX_WTCR_WTIS(rv) extract32(rv, 4, 2)
69#define NPCM7XX_WTCR_WTIF BIT(3)
70#define NPCM7XX_WTCR_WTRF BIT(2)
71#define NPCM7XX_WTCR_WTRE BIT(1)
72#define NPCM7XX_WTCR_WTR BIT(0)
73
63/*
74/*
75 * The number of clock cycles between interrupt and reset in watchdog, used
76 * by the software to handle the interrupt before system is reset.
77 */
78#define NPCM7XX_WATCHDOG_INTERRUPT_TO_RESET_CYCLES 1024
79
80/* Start or resume the timer. */
81static void npcm7xx_timer_start(NPCM7xxBaseTimer *t)
82{
83 int64_t now;
84
85 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
86 t->expires_ns = now + t->remaining_ns;
87 timer_mod(&t->qtimer, t->expires_ns);
88}
89
90/* Stop counting. Record the time remaining so we can continue later. */
91static void npcm7xx_timer_pause(NPCM7xxBaseTimer *t)
92{
93 int64_t now;
94
95 timer_del(&t->qtimer);
96 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
97 t->remaining_ns = t->expires_ns - now;
98}
99
100/* Delete the timer and reset it to default state. */
101static void npcm7xx_timer_clear(NPCM7xxBaseTimer *t)
102{
103 timer_del(&t->qtimer);
104 t->expires_ns = 0;
105 t->remaining_ns = 0;
106}
107
108/*
64 * Returns the index of timer in the tc->timer array. This can be used to
65 * locate the registers that belong to this timer.
66 */
67static int npcm7xx_timer_index(NPCM7xxTimerCtrlState *tc, NPCM7xxTimer *timer)
68{
69 int index = timer - tc->timer;
70
71 g_assert(index >= 0 && index < NPCM7XX_TIMERS_PER_CTRL);

--- 25 unchanged lines hidden (view full) ---

97 int64_t count;
98
99 count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ);
100 count /= npcm7xx_tcsr_prescaler(t->tcsr);
101
102 return count;
103}
104
109 * Returns the index of timer in the tc->timer array. This can be used to
110 * locate the registers that belong to this timer.
111 */
112static int npcm7xx_timer_index(NPCM7xxTimerCtrlState *tc, NPCM7xxTimer *timer)
113{
114 int index = timer - tc->timer;
115
116 g_assert(index >= 0 && index < NPCM7XX_TIMERS_PER_CTRL);

--- 25 unchanged lines hidden (view full) ---

142 int64_t count;
143
144 count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ);
145 count /= npcm7xx_tcsr_prescaler(t->tcsr);
146
147 return count;
148}
149
150static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
151{
152 switch (NPCM7XX_WTCR_WTCLK(t->wtcr)) {
153 case 0:
154 return 1;
155 case 1:
156 return 256;
157 case 2:
158 return 2048;
159 case 3:
160 return 65536;
161 default:
162 g_assert_not_reached();
163 }
164}
165
166static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
167 int64_t cycles)
168{
169 uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t);
170 int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles;
171
172 /*
173 * The reset function always clears the current timer. The caller of the
174 * this needs to decide whether to start the watchdog timer based on
175 * specific flag in WTCR.
176 */
177 npcm7xx_timer_clear(&t->base_timer);
178
179 ns *= prescaler;
180 t->base_timer.remaining_ns = ns;
181}
182
183static void npcm7xx_watchdog_timer_reset(NPCM7xxWatchdogTimer *t)
184{
185 int64_t cycles = 1;
186 uint32_t s = NPCM7XX_WTCR_WTIS(t->wtcr);
187
188 g_assert(s <= 3);
189
190 cycles <<= NPCM7XX_WATCHDOG_BASETIME_SHIFT;
191 cycles <<= 2 * s;
192
193 npcm7xx_watchdog_timer_reset_cycles(t, cycles);
194}
195
105/*
106 * Raise the interrupt line if there's a pending interrupt and interrupts are
107 * enabled for this timer. If not, lower it.
108 */
109static void npcm7xx_timer_check_interrupt(NPCM7xxTimer *t)
110{
111 NPCM7xxTimerCtrlState *tc = t->ctrl;
112 int index = npcm7xx_timer_index(tc, t);
113 bool pending = (t->tcsr & NPCM7XX_TCSR_IE) && (tc->tisr & BIT(index));
114
115 qemu_set_irq(t->irq, pending);
116 trace_npcm7xx_timer_irq(DEVICE(tc)->canonical_path, index, pending);
117}
118
196/*
197 * Raise the interrupt line if there's a pending interrupt and interrupts are
198 * enabled for this timer. If not, lower it.
199 */
200static void npcm7xx_timer_check_interrupt(NPCM7xxTimer *t)
201{
202 NPCM7xxTimerCtrlState *tc = t->ctrl;
203 int index = npcm7xx_timer_index(tc, t);
204 bool pending = (t->tcsr & NPCM7XX_TCSR_IE) && (tc->tisr & BIT(index));
205
206 qemu_set_irq(t->irq, pending);
207 trace_npcm7xx_timer_irq(DEVICE(tc)->canonical_path, index, pending);
208}
209
119/* Start or resume the timer. */
120static void npcm7xx_timer_start(NPCM7xxTimer *t)
121{
122 int64_t now;
123
124 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
125 t->expires_ns = now + t->remaining_ns;
126 timer_mod(&t->qtimer, t->expires_ns);
127}
128
129/*
130 * Called when the counter reaches zero. Sets the interrupt flag, and either
131 * restarts or disables the timer.
132 */
133static void npcm7xx_timer_reached_zero(NPCM7xxTimer *t)
134{
135 NPCM7xxTimerCtrlState *tc = t->ctrl;
136 int index = npcm7xx_timer_index(tc, t);
137
138 tc->tisr |= BIT(index);
139
140 if (t->tcsr & NPCM7XX_TCSR_PERIODIC) {
210/*
211 * Called when the counter reaches zero. Sets the interrupt flag, and either
212 * restarts or disables the timer.
213 */
214static void npcm7xx_timer_reached_zero(NPCM7xxTimer *t)
215{
216 NPCM7xxTimerCtrlState *tc = t->ctrl;
217 int index = npcm7xx_timer_index(tc, t);
218
219 tc->tisr |= BIT(index);
220
221 if (t->tcsr & NPCM7XX_TCSR_PERIODIC) {
141 t->remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
222 t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
142 if (t->tcsr & NPCM7XX_TCSR_CEN) {
223 if (t->tcsr & NPCM7XX_TCSR_CEN) {
143 npcm7xx_timer_start(t);
224 npcm7xx_timer_start(&t->base_timer);
144 }
145 } else {
146 t->tcsr &= ~(NPCM7XX_TCSR_CEN | NPCM7XX_TCSR_CACT);
147 }
148
149 npcm7xx_timer_check_interrupt(t);
150}
151
225 }
226 } else {
227 t->tcsr &= ~(NPCM7XX_TCSR_CEN | NPCM7XX_TCSR_CACT);
228 }
229
230 npcm7xx_timer_check_interrupt(t);
231}
232
152/* Stop counting. Record the time remaining so we can continue later. */
153static void npcm7xx_timer_pause(NPCM7xxTimer *t)
154{
155 int64_t now;
156
233
157 timer_del(&t->qtimer);
158 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
159 t->remaining_ns = t->expires_ns - now;
160}
161
162/*
163 * Restart the timer from its initial value. If the timer was enabled and stays
164 * enabled, adjust the QEMU timer according to the new count. If the timer is
165 * transitioning from disabled to enabled, the caller is expected to start the
166 * timer later.
167 */
168static void npcm7xx_timer_restart(NPCM7xxTimer *t, uint32_t old_tcsr)
169{
234/*
235 * Restart the timer from its initial value. If the timer was enabled and stays
236 * enabled, adjust the QEMU timer according to the new count. If the timer is
237 * transitioning from disabled to enabled, the caller is expected to start the
238 * timer later.
239 */
240static void npcm7xx_timer_restart(NPCM7xxTimer *t, uint32_t old_tcsr)
241{
170 t->remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
242 t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
171
172 if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) {
243
244 if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) {
173 npcm7xx_timer_start(t);
245 npcm7xx_timer_start(&t->base_timer);
174 }
175}
176
177/* Register read and write handlers */
178
179static uint32_t npcm7xx_timer_read_tdr(NPCM7xxTimer *t)
180{
181 if (t->tcsr & NPCM7XX_TCSR_CEN) {
182 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
183
246 }
247}
248
249/* Register read and write handlers */
250
251static uint32_t npcm7xx_timer_read_tdr(NPCM7xxTimer *t)
252{
253 if (t->tcsr & NPCM7XX_TCSR_CEN) {
254 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
255
184 return npcm7xx_timer_ns_to_count(t, t->expires_ns - now);
256 return npcm7xx_timer_ns_to_count(t, t->base_timer.expires_ns - now);
185 }
186
257 }
258
187 return npcm7xx_timer_ns_to_count(t, t->remaining_ns);
259 return npcm7xx_timer_ns_to_count(t, t->base_timer.remaining_ns);
188}
189
190static void npcm7xx_timer_write_tcsr(NPCM7xxTimer *t, uint32_t new_tcsr)
191{
192 uint32_t old_tcsr = t->tcsr;
193 uint32_t tdr;
194
195 if (new_tcsr & NPCM7XX_TCSR_RSVD) {

--- 15 unchanged lines hidden (view full) ---

211
212 /* Calculate the value of TDR before potentially changing the prescaler. */
213 tdr = npcm7xx_timer_read_tdr(t);
214
215 t->tcsr = (t->tcsr & NPCM7XX_TCSR_CACT) | new_tcsr;
216
217 if (npcm7xx_tcsr_prescaler(old_tcsr) != npcm7xx_tcsr_prescaler(new_tcsr)) {
218 /* Recalculate time remaining based on the current TDR value. */
260}
261
262static void npcm7xx_timer_write_tcsr(NPCM7xxTimer *t, uint32_t new_tcsr)
263{
264 uint32_t old_tcsr = t->tcsr;
265 uint32_t tdr;
266
267 if (new_tcsr & NPCM7XX_TCSR_RSVD) {

--- 15 unchanged lines hidden (view full) ---

283
284 /* Calculate the value of TDR before potentially changing the prescaler. */
285 tdr = npcm7xx_timer_read_tdr(t);
286
287 t->tcsr = (t->tcsr & NPCM7XX_TCSR_CACT) | new_tcsr;
288
289 if (npcm7xx_tcsr_prescaler(old_tcsr) != npcm7xx_tcsr_prescaler(new_tcsr)) {
290 /* Recalculate time remaining based on the current TDR value. */
219 t->remaining_ns = npcm7xx_timer_count_to_ns(t, tdr);
291 t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, tdr);
220 if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) {
292 if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) {
221 npcm7xx_timer_start(t);
293 npcm7xx_timer_start(&t->base_timer);
222 }
223 }
224
225 if ((old_tcsr ^ new_tcsr) & NPCM7XX_TCSR_IE) {
226 npcm7xx_timer_check_interrupt(t);
227 }
228 if (new_tcsr & NPCM7XX_TCSR_CRST) {
229 npcm7xx_timer_restart(t, old_tcsr);
230 t->tcsr &= ~NPCM7XX_TCSR_CRST;
231 }
232 if ((old_tcsr ^ new_tcsr) & NPCM7XX_TCSR_CEN) {
233 if (new_tcsr & NPCM7XX_TCSR_CEN) {
234 t->tcsr |= NPCM7XX_TCSR_CACT;
294 }
295 }
296
297 if ((old_tcsr ^ new_tcsr) & NPCM7XX_TCSR_IE) {
298 npcm7xx_timer_check_interrupt(t);
299 }
300 if (new_tcsr & NPCM7XX_TCSR_CRST) {
301 npcm7xx_timer_restart(t, old_tcsr);
302 t->tcsr &= ~NPCM7XX_TCSR_CRST;
303 }
304 if ((old_tcsr ^ new_tcsr) & NPCM7XX_TCSR_CEN) {
305 if (new_tcsr & NPCM7XX_TCSR_CEN) {
306 t->tcsr |= NPCM7XX_TCSR_CACT;
235 npcm7xx_timer_start(t);
307 npcm7xx_timer_start(&t->base_timer);
236 } else {
237 t->tcsr &= ~NPCM7XX_TCSR_CACT;
308 } else {
309 t->tcsr &= ~NPCM7XX_TCSR_CACT;
238 npcm7xx_timer_pause(t);
239 if (t->remaining_ns <= 0) {
310 npcm7xx_timer_pause(&t->base_timer);
311 if (t->base_timer.remaining_ns <= 0) {
240 npcm7xx_timer_reached_zero(t);
241 }
242 }
243 }
244}
245
246static void npcm7xx_timer_write_ticr(NPCM7xxTimer *t, uint32_t new_ticr)
247{

--- 6 unchanged lines hidden (view full) ---

254{
255 int i;
256
257 s->tisr &= ~value;
258 for (i = 0; i < ARRAY_SIZE(s->timer); i++) {
259 if (value & (1U << i)) {
260 npcm7xx_timer_check_interrupt(&s->timer[i]);
261 }
312 npcm7xx_timer_reached_zero(t);
313 }
314 }
315 }
316}
317
318static void npcm7xx_timer_write_ticr(NPCM7xxTimer *t, uint32_t new_ticr)
319{

--- 6 unchanged lines hidden (view full) ---

326{
327 int i;
328
329 s->tisr &= ~value;
330 for (i = 0; i < ARRAY_SIZE(s->timer); i++) {
331 if (value & (1U << i)) {
332 npcm7xx_timer_check_interrupt(&s->timer[i]);
333 }
334
262 }
263}
264
335 }
336}
337
338static void npcm7xx_timer_write_wtcr(NPCM7xxWatchdogTimer *t, uint32_t new_wtcr)
339{
340 uint32_t old_wtcr = t->wtcr;
341
342 /*
343 * WTIF and WTRF are cleared by writing 1. Writing 0 makes these bits
344 * unchanged.
345 */
346 if (new_wtcr & NPCM7XX_WTCR_WTIF) {
347 new_wtcr &= ~NPCM7XX_WTCR_WTIF;
348 } else if (old_wtcr & NPCM7XX_WTCR_WTIF) {
349 new_wtcr |= NPCM7XX_WTCR_WTIF;
350 }
351 if (new_wtcr & NPCM7XX_WTCR_WTRF) {
352 new_wtcr &= ~NPCM7XX_WTCR_WTRF;
353 } else if (old_wtcr & NPCM7XX_WTCR_WTRF) {
354 new_wtcr |= NPCM7XX_WTCR_WTRF;
355 }
356
357 t->wtcr = new_wtcr;
358
359 if (new_wtcr & NPCM7XX_WTCR_WTR) {
360 t->wtcr &= ~NPCM7XX_WTCR_WTR;
361 npcm7xx_watchdog_timer_reset(t);
362 if (new_wtcr & NPCM7XX_WTCR_WTE) {
363 npcm7xx_timer_start(&t->base_timer);
364 }
365 } else if ((old_wtcr ^ new_wtcr) & NPCM7XX_WTCR_WTE) {
366 if (new_wtcr & NPCM7XX_WTCR_WTE) {
367 npcm7xx_timer_start(&t->base_timer);
368 } else {
369 npcm7xx_timer_pause(&t->base_timer);
370 }
371 }
372
373}
374
265static hwaddr npcm7xx_tcsr_index(hwaddr reg)
266{
267 switch (reg) {
268 case NPCM7XX_TIMER_TCSR0:
269 return 0;
270 case NPCM7XX_TIMER_TCSR1:
271 return 1;
272 case NPCM7XX_TIMER_TCSR2:

--- 75 unchanged lines hidden (view full) ---

348 value = npcm7xx_timer_read_tdr(&s->timer[npcm7xx_tdr_index(reg)]);
349 break;
350
351 case NPCM7XX_TIMER_TISR:
352 value = s->tisr;
353 break;
354
355 case NPCM7XX_TIMER_WTCR:
375static hwaddr npcm7xx_tcsr_index(hwaddr reg)
376{
377 switch (reg) {
378 case NPCM7XX_TIMER_TCSR0:
379 return 0;
380 case NPCM7XX_TIMER_TCSR1:
381 return 1;
382 case NPCM7XX_TIMER_TCSR2:

--- 75 unchanged lines hidden (view full) ---

458 value = npcm7xx_timer_read_tdr(&s->timer[npcm7xx_tdr_index(reg)]);
459 break;
460
461 case NPCM7XX_TIMER_TISR:
462 value = s->tisr;
463 break;
464
465 case NPCM7XX_TIMER_WTCR:
356 value = s->wtcr;
466 value = s->watchdog_timer.wtcr;
357 break;
358
359 default:
360 qemu_log_mask(LOG_GUEST_ERROR,
361 "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
362 __func__, offset);
363 break;
364 }

--- 39 unchanged lines hidden (view full) ---

404 __func__, offset);
405 return;
406
407 case NPCM7XX_TIMER_TISR:
408 npcm7xx_timer_write_tisr(s, value);
409 return;
410
411 case NPCM7XX_TIMER_WTCR:
467 break;
468
469 default:
470 qemu_log_mask(LOG_GUEST_ERROR,
471 "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
472 __func__, offset);
473 break;
474 }

--- 39 unchanged lines hidden (view full) ---

514 __func__, offset);
515 return;
516
517 case NPCM7XX_TIMER_TISR:
518 npcm7xx_timer_write_tisr(s, value);
519 return;
520
521 case NPCM7XX_TIMER_WTCR:
412 qemu_log_mask(LOG_UNIMP, "%s: WTCR write not implemented: 0x%08x\n",
413 __func__, value);
522 npcm7xx_timer_write_wtcr(&s->watchdog_timer, value);
414 return;
415 }
416
417 qemu_log_mask(LOG_GUEST_ERROR,
418 "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
419 __func__, offset);
420}
421

--- 21 unchanged lines hidden (view full) ---

443static void npcm7xx_timer_enter_reset(Object *obj, ResetType type)
444{
445 NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
446 int i;
447
448 for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
449 NPCM7xxTimer *t = &s->timer[i];
450
523 return;
524 }
525
526 qemu_log_mask(LOG_GUEST_ERROR,
527 "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
528 __func__, offset);
529}
530

--- 21 unchanged lines hidden (view full) ---

552static void npcm7xx_timer_enter_reset(Object *obj, ResetType type)
553{
554 NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
555 int i;
556
557 for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
558 NPCM7xxTimer *t = &s->timer[i];
559
451 timer_del(&t->qtimer);
452 t->expires_ns = 0;
453 t->remaining_ns = 0;
560 npcm7xx_timer_clear(&t->base_timer);
454 t->tcsr = 0x00000005;
455 t->ticr = 0x00000000;
456 }
457
458 s->tisr = 0x00000000;
561 t->tcsr = 0x00000005;
562 t->ticr = 0x00000000;
563 }
564
565 s->tisr = 0x00000000;
459 s->wtcr = 0x00000400;
566 /*
567 * Set WTCLK to 1(default) and reset all flags except WTRF.
568 * WTRF is not reset during a core domain reset.
569 */
570 s->watchdog_timer.wtcr = 0x00000400 | (s->watchdog_timer.wtcr &
571 NPCM7XX_WTCR_WTRF);
460}
461
572}
573
574static void npcm7xx_watchdog_timer_expired(void *opaque)
575{
576 NPCM7xxWatchdogTimer *t = opaque;
577
578 if (t->wtcr & NPCM7XX_WTCR_WTE) {
579 if (t->wtcr & NPCM7XX_WTCR_WTIF) {
580 if (t->wtcr & NPCM7XX_WTCR_WTRE) {
581 t->wtcr |= NPCM7XX_WTCR_WTRF;
582 /* send reset signal to CLK module*/
583 qemu_irq_raise(t->reset_signal);
584 }
585 } else {
586 t->wtcr |= NPCM7XX_WTCR_WTIF;
587 if (t->wtcr & NPCM7XX_WTCR_WTIE) {
588 /* send interrupt */
589 qemu_irq_raise(t->irq);
590 }
591 npcm7xx_watchdog_timer_reset_cycles(t,
592 NPCM7XX_WATCHDOG_INTERRUPT_TO_RESET_CYCLES);
593 npcm7xx_timer_start(&t->base_timer);
594 }
595 }
596}
597
462static void npcm7xx_timer_hold_reset(Object *obj)
463{
464 NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
465 int i;
466
467 for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
468 qemu_irq_lower(s->timer[i].irq);
469 }
598static void npcm7xx_timer_hold_reset(Object *obj)
599{
600 NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
601 int i;
602
603 for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
604 qemu_irq_lower(s->timer[i].irq);
605 }
606 qemu_irq_lower(s->watchdog_timer.irq);
470}
471
472static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
473{
474 NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);
475 SysBusDevice *sbd = &s->parent;
476 int i;
607}
608
609static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
610{
611 NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);
612 SysBusDevice *sbd = &s->parent;
613 int i;
614 NPCM7xxWatchdogTimer *w;
477
478 for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
479 NPCM7xxTimer *t = &s->timer[i];
480 t->ctrl = s;
615
616 for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
617 NPCM7xxTimer *t = &s->timer[i];
618 t->ctrl = s;
481 timer_init_ns(&t->qtimer, QEMU_CLOCK_VIRTUAL, npcm7xx_timer_expired, t);
619 timer_init_ns(&t->base_timer.qtimer, QEMU_CLOCK_VIRTUAL,
620 npcm7xx_timer_expired, t);
482 sysbus_init_irq(sbd, &t->irq);
483 }
484
621 sysbus_init_irq(sbd, &t->irq);
622 }
623
624 w = &s->watchdog_timer;
625 w->ctrl = s;
626 timer_init_ns(&w->base_timer.qtimer, QEMU_CLOCK_VIRTUAL,
627 npcm7xx_watchdog_timer_expired, w);
628 sysbus_init_irq(sbd, &w->irq);
629
485 memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s,
486 TYPE_NPCM7XX_TIMER, 4 * KiB);
487 sysbus_init_mmio(sbd, &s->iomem);
630 memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s,
631 TYPE_NPCM7XX_TIMER, 4 * KiB);
632 sysbus_init_mmio(sbd, &s->iomem);
633 qdev_init_gpio_out_named(dev, &w->reset_signal,
634 NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1);
488}
489
635}
636
490static const VMStateDescription vmstate_npcm7xx_timer = {
491 .name = "npcm7xx-timer",
637static const VMStateDescription vmstate_npcm7xx_base_timer = {
638 .name = "npcm7xx-base-timer",
492 .version_id = 0,
493 .minimum_version_id = 0,
494 .fields = (VMStateField[]) {
639 .version_id = 0,
640 .minimum_version_id = 0,
641 .fields = (VMStateField[]) {
495 VMSTATE_TIMER(qtimer, NPCM7xxTimer),
496 VMSTATE_INT64(expires_ns, NPCM7xxTimer),
497 VMSTATE_INT64(remaining_ns, NPCM7xxTimer),
642 VMSTATE_TIMER(qtimer, NPCM7xxBaseTimer),
643 VMSTATE_INT64(expires_ns, NPCM7xxBaseTimer),
644 VMSTATE_INT64(remaining_ns, NPCM7xxBaseTimer),
645 VMSTATE_END_OF_LIST(),
646 },
647};
648
649static const VMStateDescription vmstate_npcm7xx_timer = {
650 .name = "npcm7xx-timer",
651 .version_id = 1,
652 .minimum_version_id = 1,
653 .fields = (VMStateField[]) {
654 VMSTATE_STRUCT(base_timer, NPCM7xxTimer,
655 0, vmstate_npcm7xx_base_timer,
656 NPCM7xxBaseTimer),
498 VMSTATE_UINT32(tcsr, NPCM7xxTimer),
499 VMSTATE_UINT32(ticr, NPCM7xxTimer),
500 VMSTATE_END_OF_LIST(),
501 },
502};
503
657 VMSTATE_UINT32(tcsr, NPCM7xxTimer),
658 VMSTATE_UINT32(ticr, NPCM7xxTimer),
659 VMSTATE_END_OF_LIST(),
660 },
661};
662
504static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
505 .name = "npcm7xx-timer-ctrl",
663static const VMStateDescription vmstate_npcm7xx_watchdog_timer = {
664 .name = "npcm7xx-watchdog-timer",
506 .version_id = 0,
507 .minimum_version_id = 0,
508 .fields = (VMStateField[]) {
665 .version_id = 0,
666 .minimum_version_id = 0,
667 .fields = (VMStateField[]) {
668 VMSTATE_STRUCT(base_timer, NPCM7xxWatchdogTimer,
669 0, vmstate_npcm7xx_base_timer,
670 NPCM7xxBaseTimer),
671 VMSTATE_UINT32(wtcr, NPCM7xxWatchdogTimer),
672 VMSTATE_END_OF_LIST(),
673 },
674};
675
676static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
677 .name = "npcm7xx-timer-ctrl",
678 .version_id = 1,
679 .minimum_version_id = 1,
680 .fields = (VMStateField[]) {
509 VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
681 VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
510 VMSTATE_UINT32(wtcr, NPCM7xxTimerCtrlState),
511 VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,
512 NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,
513 NPCM7xxTimer),
682 VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,
683 NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,
684 NPCM7xxTimer),
685 VMSTATE_STRUCT(watchdog_timer, NPCM7xxTimerCtrlState,
686 0, vmstate_npcm7xx_watchdog_timer,
687 NPCM7xxWatchdogTimer),
514 VMSTATE_END_OF_LIST(),
515 },
516};
517
518static void npcm7xx_timer_class_init(ObjectClass *klass, void *data)
519{
520 ResettableClass *rc = RESETTABLE_CLASS(klass);
521 DeviceClass *dc = DEVICE_CLASS(klass);

--- 22 unchanged lines hidden --- 		688 VMSTATE_END_OF_LIST(),
689 },
690};
691
692static void npcm7xx_timer_class_init(ObjectClass *klass, void *data)
693{
694 ResettableClass *rc = RESETTABLE_CLASS(klass);
695 DeviceClass *dc = DEVICE_CLASS(klass);

--- 22 unchanged lines hidden ---