ibex_timer.c (28ca4689ae94a27a6a337546425cda30d0e885c3) ibex_timer.c (dda94e5c66e4c48c3709acf5532c295a80845730)
1/*
2 * QEMU lowRISC Ibex Timer device
3 *
4 * Copyright (c) 2021 Western Digital
5 *
6 * For details check the documentation here:
7 * https://docs.opentitan.org/hw/ip/rv_timer/doc/
8 *

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29#include "qemu/log.h"
30#include "qemu/timer.h"
31#include "hw/timer/ibex_timer.h"
32#include "hw/irq.h"
33#include "hw/qdev-properties.h"
34#include "target/riscv/cpu.h"
35#include "migration/vmstate.h"
36
1/*
2 * QEMU lowRISC Ibex Timer device
3 *
4 * Copyright (c) 2021 Western Digital
5 *
6 * For details check the documentation here:
7 * https://docs.opentitan.org/hw/ip/rv_timer/doc/
8 *

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29#include "qemu/log.h"
30#include "qemu/timer.h"
31#include "hw/timer/ibex_timer.h"
32#include "hw/irq.h"
33#include "hw/qdev-properties.h"
34#include "target/riscv/cpu.h"
35#include "migration/vmstate.h"
36
37REG32(CTRL, 0x00)
37REG32(ALERT_TEST, 0x00)
38 FIELD(ALERT_TEST, FATAL_FAULT, 0, 1)
39REG32(CTRL, 0x04)
38 FIELD(CTRL, ACTIVE, 0, 1)
39REG32(CFG0, 0x100)
40 FIELD(CFG0, PRESCALE, 0, 12)
41 FIELD(CFG0, STEP, 16, 8)
42REG32(LOWER0, 0x104)
43REG32(UPPER0, 0x108)
44REG32(COMPARE_LOWER0, 0x10C)
45REG32(COMPARE_UPPER0, 0x110)

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137static uint64_t ibex_timer_read(void *opaque, hwaddr addr,
138 unsigned int size)
139{
140 IbexTimerState *s = opaque;
141 uint64_t now = cpu_riscv_read_rtc(s->timebase_freq);
142 uint64_t retvalue = 0;
143
144 switch (addr >> 2) {
40 FIELD(CTRL, ACTIVE, 0, 1)
41REG32(CFG0, 0x100)
42 FIELD(CFG0, PRESCALE, 0, 12)
43 FIELD(CFG0, STEP, 16, 8)
44REG32(LOWER0, 0x104)
45REG32(UPPER0, 0x108)
46REG32(COMPARE_LOWER0, 0x10C)
47REG32(COMPARE_UPPER0, 0x110)

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139static uint64_t ibex_timer_read(void *opaque, hwaddr addr,
140 unsigned int size)
141{
142 IbexTimerState *s = opaque;
143 uint64_t now = cpu_riscv_read_rtc(s->timebase_freq);
144 uint64_t retvalue = 0;
145
146 switch (addr >> 2) {
147 case R_ALERT_TEST:
148 qemu_log_mask(LOG_GUEST_ERROR,
149 "Attempted to read ALERT_TEST, a write only register");
150 break;
145 case R_CTRL:
146 retvalue = s->timer_ctrl;
147 break;
148 case R_CFG0:
149 retvalue = s->timer_cfg0;
150 break;
151 case R_LOWER0:
152 retvalue = now;

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181
182static void ibex_timer_write(void *opaque, hwaddr addr,
183 uint64_t val64, unsigned int size)
184{
185 IbexTimerState *s = opaque;
186 uint32_t val = val64;
187
188 switch (addr >> 2) {
151 case R_CTRL:
152 retvalue = s->timer_ctrl;
153 break;
154 case R_CFG0:
155 retvalue = s->timer_cfg0;
156 break;
157 case R_LOWER0:
158 retvalue = now;

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187
188static void ibex_timer_write(void *opaque, hwaddr addr,
189 uint64_t val64, unsigned int size)
190{
191 IbexTimerState *s = opaque;
192 uint32_t val = val64;
193
194 switch (addr >> 2) {
195 case R_ALERT_TEST:
196 qemu_log_mask(LOG_UNIMP, "Alert triggering not supported");
197 break;
189 case R_CTRL:
190 s->timer_ctrl = val;
191 break;
192 case R_CFG0:
193 qemu_log_mask(LOG_UNIMP, "Changing prescale or step not supported");
194 s->timer_cfg0 = val;
195 break;
196 case R_LOWER0:

--- 112 unchanged lines hidden --- 		198 case R_CTRL:
199 s->timer_ctrl = val;
200 break;
201 case R_CFG0:
202 qemu_log_mask(LOG_UNIMP, "Changing prescale or step not supported");
203 s->timer_cfg0 = val;
204 break;
205 case R_LOWER0:

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