exynos4210_mct.c (c3ab4c9cf24ec9efb9c6d82b6027c0587d3081fa) exynos4210_mct.c (81e1010d0fbfaa5992cffa88e1797af36cc438ef)
1/*
2 * Samsung exynos4210 Multi Core timer
3 *
4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
5 * All rights reserved.
6 *
7 * Evgeny Voevodin <e.voevodin@samsung.com>
8 *

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235 uint32_t tcon;
236 uint32_t int_cstat;
237 uint32_t int_enb;
238 uint32_t wstat;
239 } reg;
240
241} Exynos4210MCTLT;
242
1/*
2 * Samsung exynos4210 Multi Core timer
3 *
4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
5 * All rights reserved.
6 *
7 * Evgeny Voevodin <e.voevodin@samsung.com>
8 *

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235 uint32_t tcon;
236 uint32_t int_cstat;
237 uint32_t int_enb;
238 uint32_t wstat;
239 } reg;
240
241} Exynos4210MCTLT;
242
243#define TYPE_EXYNOS4210_MCT "exynos4210.mct"
244#define EXYNOS4210_MCT(obj) \
245 OBJECT_CHECK(Exynos4210MCTState, (obj), TYPE_EXYNOS4210_MCT)
246
243typedef struct Exynos4210MCTState {
247typedef struct Exynos4210MCTState {
244 SysBusDevice busdev;
248 SysBusDevice parent_obj;
249
245 MemoryRegion iomem;
246
247 /* Registers */
248 uint32_t reg_mct_cfg;
249
250 Exynos4210MCTLT l_timer[2];
251 Exynos4210MCTGT g_timer;
252

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950 ptimer_set_freq(s->l_timer[1].tick_timer.ptimer_tick, s->freq);
951 ptimer_set_freq(s->l_timer[1].ptimer_frc, s->freq);
952 }
953}
954
955/* set defaul_timer values for all fields */
956static void exynos4210_mct_reset(DeviceState *d)
957{
250 MemoryRegion iomem;
251
252 /* Registers */
253 uint32_t reg_mct_cfg;
254
255 Exynos4210MCTLT l_timer[2];
256 Exynos4210MCTGT g_timer;
257

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955 ptimer_set_freq(s->l_timer[1].tick_timer.ptimer_tick, s->freq);
956 ptimer_set_freq(s->l_timer[1].ptimer_frc, s->freq);
957 }
958}
959
960/* set defaul_timer values for all fields */
961static void exynos4210_mct_reset(DeviceState *d)
962{
958 Exynos4210MCTState *s = (Exynos4210MCTState *)d;
963 Exynos4210MCTState *s = EXYNOS4210_MCT(d);
959 uint32_t i;
960
961 s->reg_mct_cfg = 0;
962
963 /* global timer */
964 memset(&s->g_timer.reg, 0, sizeof(s->g_timer.reg));
965 exynos4210_gfrc_stop(&s->g_timer);
966

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1419 .write = exynos4210_mct_write,
1420 .endianness = DEVICE_NATIVE_ENDIAN,
1421};
1422
1423/* MCT init */
1424static int exynos4210_mct_init(SysBusDevice *dev)
1425{
1426 int i;
964 uint32_t i;
965
966 s->reg_mct_cfg = 0;
967
968 /* global timer */
969 memset(&s->g_timer.reg, 0, sizeof(s->g_timer.reg));
970 exynos4210_gfrc_stop(&s->g_timer);
971

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1424 .write = exynos4210_mct_write,
1425 .endianness = DEVICE_NATIVE_ENDIAN,
1426};
1427
1428/* MCT init */
1429static int exynos4210_mct_init(SysBusDevice *dev)
1430{
1431 int i;
1427 Exynos4210MCTState *s = FROM_SYSBUS(Exynos4210MCTState, dev);
1432 Exynos4210MCTState *s = EXYNOS4210_MCT(dev);
1428 QEMUBH *bh[2];
1429
1430 /* Global timer */
1431 bh[0] = qemu_bh_new(exynos4210_gfrc_event, s);
1432 s->g_timer.ptimer_frc = ptimer_init(bh[0]);
1433 memset(&s->g_timer.reg, 0, sizeof(struct gregs));
1434
1435 /* Local timers */

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1462 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1463
1464 k->init = exynos4210_mct_init;
1465 dc->reset = exynos4210_mct_reset;
1466 dc->vmsd = &vmstate_exynos4210_mct_state;
1467}
1468
1469static const TypeInfo exynos4210_mct_info = {
1433 QEMUBH *bh[2];
1434
1435 /* Global timer */
1436 bh[0] = qemu_bh_new(exynos4210_gfrc_event, s);
1437 s->g_timer.ptimer_frc = ptimer_init(bh[0]);
1438 memset(&s->g_timer.reg, 0, sizeof(struct gregs));
1439
1440 /* Local timers */

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1467 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1468
1469 k->init = exynos4210_mct_init;
1470 dc->reset = exynos4210_mct_reset;
1471 dc->vmsd = &vmstate_exynos4210_mct_state;
1472}
1473
1474static const TypeInfo exynos4210_mct_info = {
1470 .name = "exynos4210.mct",
1475 .name = TYPE_EXYNOS4210_MCT,
1471 .parent = TYPE_SYS_BUS_DEVICE,
1472 .instance_size = sizeof(Exynos4210MCTState),
1473 .class_init = exynos4210_mct_class_init,
1474};
1475
1476static void exynos4210_mct_register_types(void)
1477{
1478 type_register_static(&exynos4210_mct_info);
1479}
1480
1481type_init(exynos4210_mct_register_types)
1476 .parent = TYPE_SYS_BUS_DEVICE,
1477 .instance_size = sizeof(Exynos4210MCTState),
1478 .class_init = exynos4210_mct_class_init,
1479};
1480
1481static void exynos4210_mct_register_types(void)
1482{
1483 type_register_static(&exynos4210_mct_info);
1484}
1485
1486type_init(exynos4210_mct_register_types)