spike.c (df50424b4dcfde823047d3717abd6a61224ea205) spike.c (55c136599f512a86e3fec9f77b6b5a30a6b34cca)
1/*
2 * QEMU RISC-V Spike Board
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This provides a RISC-V Board with the following devices:
8 *

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193
194static void spike_board_init(MachineState *machine)
195{
196 const MemMapEntry *memmap = spike_memmap;
197 SpikeState *s = SPIKE_MACHINE(machine);
198 MemoryRegion *system_memory = get_system_memory();
199 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
200 target_ulong firmware_end_addr = memmap[SPIKE_DRAM].base;
1/*
2 * QEMU RISC-V Spike Board
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This provides a RISC-V Board with the following devices:
8 *

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193
194static void spike_board_init(MachineState *machine)
195{
196 const MemMapEntry *memmap = spike_memmap;
197 SpikeState *s = SPIKE_MACHINE(machine);
198 MemoryRegion *system_memory = get_system_memory();
199 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
200 target_ulong firmware_end_addr = memmap[SPIKE_DRAM].base;
201 hwaddr firmware_load_addr = memmap[SPIKE_DRAM].base;
201 target_ulong kernel_start_addr;
202 char *firmware_name;
203 uint32_t fdt_load_addr;
204 uint64_t kernel_entry;
205 char *soc_name;
206 int i, base_hartid, hart_count;
207 bool htif_custom_base = false;
208

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285 if (!htif_custom_base && machine->kernel_filename) {
286 htif_custom_base = !spike_test_elf_image(machine->kernel_filename);
287 }
288 }
289
290 /* Load firmware */
291 if (firmware_name) {
292 firmware_end_addr = riscv_load_firmware(firmware_name,
202 target_ulong kernel_start_addr;
203 char *firmware_name;
204 uint32_t fdt_load_addr;
205 uint64_t kernel_entry;
206 char *soc_name;
207 int i, base_hartid, hart_count;
208 bool htif_custom_base = false;
209

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286 if (!htif_custom_base && machine->kernel_filename) {
287 htif_custom_base = !spike_test_elf_image(machine->kernel_filename);
288 }
289 }
290
291 /* Load firmware */
292 if (firmware_name) {
293 firmware_end_addr = riscv_load_firmware(firmware_name,
293 memmap[SPIKE_DRAM].base,
294 &firmware_load_addr,
294 htif_symbol_callback);
295 g_free(firmware_name);
296 }
297
298 /* Create device tree */
299 create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]), htif_custom_base);
300
301 /* Load kernel */

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315 }
316
317 fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base,
318 memmap[SPIKE_DRAM].size,
319 machine);
320 riscv_load_fdt(fdt_load_addr, machine->fdt);
321
322 /* load the reset vector */
295 htif_symbol_callback);
296 g_free(firmware_name);
297 }
298
299 /* Create device tree */
300 create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]), htif_custom_base);
301
302 /* Load kernel */

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316 }
317
318 fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base,
319 memmap[SPIKE_DRAM].size,
320 machine);
321 riscv_load_fdt(fdt_load_addr, machine->fdt);
322
323 /* load the reset vector */
323 riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base,
324 riscv_setup_rom_reset_vec(machine, &s->soc[0], firmware_load_addr,
324 memmap[SPIKE_MROM].base,
325 memmap[SPIKE_MROM].size, kernel_entry,
326 fdt_load_addr);
327
328 /* initialize HTIF using symbols found in load_kernel */
329 htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base,
330 htif_custom_base);
331}

--- 50 unchanged lines hidden --- 		325 memmap[SPIKE_MROM].base,
326 memmap[SPIKE_MROM].size, kernel_entry,
327 fdt_load_addr);
328
329 /* initialize HTIF using symbols found in load_kernel */
330 htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base,
331 htif_custom_base);
332}

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