spike.c (d45a5270d075ea589f0b0ddcf963a5fea1f500ac) spike.c (7cfbb17f023dc014d366b2f30af852aa62a5c3b1)
1/*
2 * QEMU RISC-V Spike Board
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This provides a RISC-V Board with the following devices:
8 *

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54 uint64_t addr, size;
55 unsigned long clint_addr;
56 int cpu, socket;
57 MachineState *mc = MACHINE(s);
58 uint32_t *clint_cells;
59 uint32_t cpu_phandle, intc_phandle, phandle = 1;
60 char *name, *mem_name, *clint_name, *clust_name;
61 char *core_name, *cpu_name, *intc_name;
1/*
2 * QEMU RISC-V Spike Board
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This provides a RISC-V Board with the following devices:
8 *

--- 45 unchanged lines hidden (view full) ---

54 uint64_t addr, size;
55 unsigned long clint_addr;
56 int cpu, socket;
57 MachineState *mc = MACHINE(s);
58 uint32_t *clint_cells;
59 uint32_t cpu_phandle, intc_phandle, phandle = 1;
60 char *name, *mem_name, *clint_name, *clust_name;
61 char *core_name, *cpu_name, *intc_name;
62 static const char * const clint_compat[2] = {
63 "sifive,clint0", "riscv,clint0"
64 };
62
63 fdt = s->fdt = create_device_tree(&s->fdt_size);
64 if (!fdt) {
65 error_report("create_device_tree() failed");
66 exit(1);
67 }
68
69 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");

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147 qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
148 riscv_socket_fdt_write_id(mc, fdt, mem_name, socket);
149 g_free(mem_name);
150
151 clint_addr = memmap[SPIKE_CLINT].base +
152 (memmap[SPIKE_CLINT].size * socket);
153 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
154 qemu_fdt_add_subnode(fdt, clint_name);
65
66 fdt = s->fdt = create_device_tree(&s->fdt_size);
67 if (!fdt) {
68 error_report("create_device_tree() failed");
69 exit(1);
70 }
71
72 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");

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150 qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
151 riscv_socket_fdt_write_id(mc, fdt, mem_name, socket);
152 g_free(mem_name);
153
154 clint_addr = memmap[SPIKE_CLINT].base +
155 (memmap[SPIKE_CLINT].size * socket);
156 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
157 qemu_fdt_add_subnode(fdt, clint_name);
155 qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0");
158 qemu_fdt_setprop_string_array(fdt, clint_name, "compatible",
159 (char **)&clint_compat, ARRAY_SIZE(clint_compat));
156 qemu_fdt_setprop_cells(fdt, clint_name, "reg",
157 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
158 qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
159 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
160 riscv_socket_fdt_write_id(mc, fdt, clint_name, socket);
161
162 g_free(clint_name);
163 g_free(clint_cells);

--- 176 unchanged lines hidden --- 		160 qemu_fdt_setprop_cells(fdt, clint_name, "reg",
161 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
162 qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
163 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
164 riscv_socket_fdt_write_id(mc, fdt, clint_name, socket);
165
166 g_free(clint_name);
167 g_free(clint_cells);

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