spike.c (b11728dc3ae67ddedf34b7a4f318170e7092803c) spike.c (66247edc8b6fb36d6b905babcd795068ea989ad5)
1/*
2 * QEMU RISC-V Spike Board
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This provides a RISC-V Board with the following devices:
8 *

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327 memmap[SPIKE_MROM].size, kernel_entry,
328 fdt_load_addr);
329
330 /* initialize HTIF using symbols found in load_kernel */
331 htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base,
332 htif_custom_base);
333}
334
1/*
2 * QEMU RISC-V Spike Board
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This provides a RISC-V Board with the following devices:
8 *

--- 318 unchanged lines hidden (view full) ---

327 memmap[SPIKE_MROM].size, kernel_entry,
328 fdt_load_addr);
329
330 /* initialize HTIF using symbols found in load_kernel */
331 htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base,
332 htif_custom_base);
333}
334
335static void spike_set_signature(Object *obj, const char *val, Error **errp)
336{
337 sig_file = g_strdup(val);
338}
339
335static void spike_machine_instance_init(Object *obj)
336{
337}
338
339static void spike_machine_class_init(ObjectClass *oc, void *data)
340{
341 MachineClass *mc = MACHINE_CLASS(oc);
342
343 mc->desc = "RISC-V Spike board";
344 mc->init = spike_board_init;
345 mc->max_cpus = SPIKE_CPUS_MAX;
346 mc->is_default = true;
347 mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
348 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
349 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
350 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
351 mc->numa_mem_supported = true;
352 mc->default_ram_id = "riscv.spike.ram";
340static void spike_machine_instance_init(Object *obj)
341{
342}
343
344static void spike_machine_class_init(ObjectClass *oc, void *data)
345{
346 MachineClass *mc = MACHINE_CLASS(oc);
347
348 mc->desc = "RISC-V Spike board";
349 mc->init = spike_board_init;
350 mc->max_cpus = SPIKE_CPUS_MAX;
351 mc->is_default = true;
352 mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
353 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
354 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
355 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
356 mc->numa_mem_supported = true;
357 mc->default_ram_id = "riscv.spike.ram";
358 object_class_property_add_str(oc, "signature", NULL, spike_set_signature);
359 object_class_property_set_description(oc, "signature",
360 "File to write ACT test signature");
361 object_class_property_add_uint8_ptr(oc, "signature-granularity",
362 &line_size, OBJ_PROP_FLAG_WRITE);
363 object_class_property_set_description(oc, "signature-granularity",
364 "Size of each line in ACT signature "
365 "file");
353}
354
355static const TypeInfo spike_machine_typeinfo = {
356 .name = MACHINE_TYPE_NAME("spike"),
357 .parent = TYPE_MACHINE,
358 .class_init = spike_machine_class_init,
359 .instance_init = spike_machine_instance_init,
360 .instance_size = sizeof(SpikeState),
361};
362
363static void spike_machine_init_register_types(void)
364{
365 type_register_static(&spike_machine_typeinfo);
366}
367
368type_init(spike_machine_init_register_types)
366}
367
368static const TypeInfo spike_machine_typeinfo = {
369 .name = MACHINE_TYPE_NAME("spike"),
370 .parent = TYPE_MACHINE,
371 .class_init = spike_machine_class_init,
372 .instance_init = spike_machine_instance_init,
373 .instance_size = sizeof(SpikeState),
374};
375
376static void spike_machine_init_register_types(void)
377{
378 type_register_static(&spike_machine_typeinfo);
379}
380
381type_init(spike_machine_init_register_types)