spike.c (9d3f7108bc43e93ceef7faa27c87eea8295c33ed) spike.c (71d68c48be96366fb89f7a2dd9d82dd86bcbe542)
1/*
2 * QEMU RISC-V Spike Board
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This provides a RISC-V Board with the following devices:
8 *

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44static const MemMapEntry spike_memmap[] = {
45 [SPIKE_MROM] = { 0x1000, 0xf000 },
46 [SPIKE_HTIF] = { 0x1000000, 0x1000 },
47 [SPIKE_CLINT] = { 0x2000000, 0x10000 },
48 [SPIKE_DRAM] = { 0x80000000, 0x0 },
49};
50
51static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
1/*
2 * QEMU RISC-V Spike Board
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This provides a RISC-V Board with the following devices:
8 *

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44static const MemMapEntry spike_memmap[] = {
45 [SPIKE_MROM] = { 0x1000, 0xf000 },
46 [SPIKE_HTIF] = { 0x1000000, 0x1000 },
47 [SPIKE_CLINT] = { 0x2000000, 0x10000 },
48 [SPIKE_DRAM] = { 0x80000000, 0x0 },
49};
50
51static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
52 uint64_t mem_size, const char *cmdline, bool is_32_bit)
52 uint64_t mem_size, const char *cmdline,
53 bool is_32_bit, bool htif_custom_base)
53{
54 void *fdt;
55 uint64_t addr, size;
56 unsigned long clint_addr;
57 int cpu, socket;
58 MachineState *mc = MACHINE(s);
59 uint32_t *clint_cells;
60 uint32_t cpu_phandle, intc_phandle, phandle = 1;

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72
73 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
74 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
75 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
76 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
77
78 qemu_fdt_add_subnode(fdt, "/htif");
79 qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
54{
55 void *fdt;
56 uint64_t addr, size;
57 unsigned long clint_addr;
58 int cpu, socket;
59 MachineState *mc = MACHINE(s);
60 uint32_t *clint_cells;
61 uint32_t cpu_phandle, intc_phandle, phandle = 1;

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73
74 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
75 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
76 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
77 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
78
79 qemu_fdt_add_subnode(fdt, "/htif");
80 qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
80 if (!htif_uses_elf_symbols()) {
81 if (htif_custom_base) {
81 qemu_fdt_setprop_cells(fdt, "/htif", "reg",
82 0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size);
83 }
84
85 qemu_fdt_add_subnode(fdt, "/soc");
86 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
87 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
88 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);

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178 qemu_fdt_add_subnode(fdt, "/chosen");
179 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
180
181 if (cmdline && *cmdline) {
182 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
183 }
184}
185
82 qemu_fdt_setprop_cells(fdt, "/htif", "reg",
83 0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size);
84 }
85
86 qemu_fdt_add_subnode(fdt, "/soc");
87 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
88 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
89 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);

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179 qemu_fdt_add_subnode(fdt, "/chosen");
180 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
181
182 if (cmdline && *cmdline) {
183 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
184 }
185}
186
187static bool spike_test_elf_image(char *filename)
188{
189 Error *err = NULL;
190
191 load_elf_hdr(filename, NULL, NULL, &err);
192 if (err) {
193 error_free(err);
194 return false;
195 } else {
196 return true;
197 }
198}
199
186static void spike_board_init(MachineState *machine)
187{
188 const MemMapEntry *memmap = spike_memmap;
189 SpikeState *s = SPIKE_MACHINE(machine);
190 MemoryRegion *system_memory = get_system_memory();
191 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
200static void spike_board_init(MachineState *machine)
201{
202 const MemMapEntry *memmap = spike_memmap;
203 SpikeState *s = SPIKE_MACHINE(machine);
204 MemoryRegion *system_memory = get_system_memory();
205 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
192 target_ulong firmware_end_addr, kernel_start_addr;
193 const char *firmware_name;
206 target_ulong firmware_end_addr = memmap[SPIKE_DRAM].base;
207 target_ulong kernel_start_addr;
208 char *firmware_name;
194 uint32_t fdt_load_addr;
195 uint64_t kernel_entry;
196 char *soc_name;
197 int i, base_hartid, hart_count;
209 uint32_t fdt_load_addr;
210 uint64_t kernel_entry;
211 char *soc_name;
212 int i, base_hartid, hart_count;
213 bool htif_custom_base = false;
198
199 /* Check socket count limit */
200 if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) {
201 error_report("number of sockets/nodes should be less than %d",
202 SPIKE_SOCKETS_MAX);
203 exit(1);
204 }
205

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251 machine->ram);
252
253 /* boot rom */
254 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
255 memmap[SPIKE_MROM].size, &error_fatal);
256 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
257 mask_rom);
258
214
215 /* Check socket count limit */
216 if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) {
217 error_report("number of sockets/nodes should be less than %d",
218 SPIKE_SOCKETS_MAX);
219 exit(1);
220 }
221

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267 machine->ram);
268
269 /* boot rom */
270 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
271 memmap[SPIKE_MROM].size, &error_fatal);
272 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
273 mask_rom);
274
259 firmware_name = riscv_default_firmware_name(&s->soc[0]);
260 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
261 memmap[SPIKE_DRAM].base,
262 htif_symbol_callback);
275 /* Find firmware */
276 firmware_name = riscv_find_firmware(machine->firmware,
277 riscv_default_firmware_name(&s->soc[0]));
263
278
279 /*
280 * Test the given firmware or kernel file to see if it is an ELF image.
281 * If it is an ELF, we assume it contains the symbols required for
282 * the HTIF console, otherwise we fall back to use the custom base
283 * passed from device tree for the HTIF console.
284 */
285 if (!firmware_name && !machine->kernel_filename) {
286 htif_custom_base = true;
287 } else {
288 if (firmware_name) {
289 htif_custom_base = !spike_test_elf_image(firmware_name);
290 }
291 if (!htif_custom_base && machine->kernel_filename) {
292 htif_custom_base = !spike_test_elf_image(machine->kernel_filename);
293 }
294 }
295
296 /* Load firmware */
297 if (firmware_name) {
298 firmware_end_addr = riscv_load_firmware(firmware_name,
299 memmap[SPIKE_DRAM].base,
300 htif_symbol_callback);
301 g_free(firmware_name);
302 }
303
264 /* Load kernel */
265 if (machine->kernel_filename) {
266 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
267 firmware_end_addr);
268
269 kernel_entry = riscv_load_kernel(machine->kernel_filename,
270 kernel_start_addr,
271 htif_symbol_callback);
272 } else {
273 /*
274 * If dynamic firmware is used, it doesn't know where is the next mode
275 * if kernel argument is not set.
276 */
277 kernel_entry = 0;
278 }
279
280 /* Create device tree */
281 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
304 /* Load kernel */
305 if (machine->kernel_filename) {
306 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
307 firmware_end_addr);
308
309 kernel_entry = riscv_load_kernel(machine->kernel_filename,
310 kernel_start_addr,
311 htif_symbol_callback);
312 } else {
313 /*
314 * If dynamic firmware is used, it doesn't know where is the next mode
315 * if kernel argument is not set.
316 */
317 kernel_entry = 0;
318 }
319
320 /* Create device tree */
321 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
282 riscv_is_32bit(&s->soc[0]));
322 riscv_is_32bit(&s->soc[0]), htif_custom_base);
283
284 /* Load initrd */
285 if (machine->kernel_filename && machine->initrd_filename) {
286 hwaddr start;
287 hwaddr end = riscv_load_initrd(machine->initrd_filename,
288 machine->ram_size, kernel_entry,
289 &start);
290 qemu_fdt_setprop_cell(s->fdt, "/chosen",

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302
303 /* load the reset vector */
304 riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base,
305 memmap[SPIKE_MROM].base,
306 memmap[SPIKE_MROM].size, kernel_entry,
307 fdt_load_addr);
308
309 /* initialize HTIF using symbols found in load_kernel */
323
324 /* Load initrd */
325 if (machine->kernel_filename && machine->initrd_filename) {
326 hwaddr start;
327 hwaddr end = riscv_load_initrd(machine->initrd_filename,
328 machine->ram_size, kernel_entry,
329 &start);
330 qemu_fdt_setprop_cell(s->fdt, "/chosen",

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342
343 /* load the reset vector */
344 riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base,
345 memmap[SPIKE_MROM].base,
346 memmap[SPIKE_MROM].size, kernel_entry,
347 fdt_load_addr);
348
349 /* initialize HTIF using symbols found in load_kernel */
310 htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base);
350 htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base,
351 htif_custom_base);
311}
312
313static void spike_machine_instance_init(Object *obj)
314{
315}
316
317static void spike_machine_class_init(ObjectClass *oc, void *data)
318{

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353
354static void spike_machine_instance_init(Object *obj)
355{
356}
357
358static void spike_machine_class_init(ObjectClass *oc, void *data)
359{

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