sifive_u.c (df50424b4dcfde823047d3717abd6a61224ea205) sifive_u.c (55c136599f512a86e3fec9f77b6b5a30a6b34cca)
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
7 *
8 * Provides a board compatible with the SiFive Freedom U SDK:

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510}
511
512static void sifive_u_machine_init(MachineState *machine)
513{
514 const MemMapEntry *memmap = sifive_u_memmap;
515 SiFiveUState *s = RISCV_U_MACHINE(machine);
516 MemoryRegion *system_memory = get_system_memory();
517 MemoryRegion *flash0 = g_new(MemoryRegion, 1);
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
7 *
8 * Provides a board compatible with the SiFive Freedom U SDK:

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510}
511
512static void sifive_u_machine_init(MachineState *machine)
513{
514 const MemMapEntry *memmap = sifive_u_memmap;
515 SiFiveUState *s = RISCV_U_MACHINE(machine);
516 MemoryRegion *system_memory = get_system_memory();
517 MemoryRegion *flash0 = g_new(MemoryRegion, 1);
518 target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
518 hwaddr start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
519 target_ulong firmware_end_addr, kernel_start_addr;
520 const char *firmware_name;
521 uint32_t start_addr_hi32 = 0x00000000;
522 int i;
523 uint32_t fdt_load_addr;
524 uint64_t kernel_entry;
525 DriveInfo *dinfo;
526 BlockBackend *blk;

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584 break;
585 default:
586 start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
587 break;
588 }
589
590 firmware_name = riscv_default_firmware_name(&s->soc.u_cpus);
591 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
519 target_ulong firmware_end_addr, kernel_start_addr;
520 const char *firmware_name;
521 uint32_t start_addr_hi32 = 0x00000000;
522 int i;
523 uint32_t fdt_load_addr;
524 uint64_t kernel_entry;
525 DriveInfo *dinfo;
526 BlockBackend *blk;

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584 break;
585 default:
586 start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
587 break;
588 }
589
590 firmware_name = riscv_default_firmware_name(&s->soc.u_cpus);
591 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
592 start_addr, NULL);
592 &start_addr, NULL);
593
594 if (machine->kernel_filename) {
595 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
596 firmware_end_addr);
597
598 kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus,
599 kernel_start_addr, true, NULL);
600 } else {

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594 if (machine->kernel_filename) {
595 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
596 firmware_end_addr);
597
598 kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus,
599 kernel_start_addr, true, NULL);
600 } else {

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