sifive_u.c (dc144fe13d336caac2f03b57f1df738e84f984ec) sifive_u.c (8590f53661ec678fd3aa97b4da212b0c00056c2e)
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
7 *
8 * Provides a board compatible with the SiFive Freedom U SDK:

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373static void sifive_u_machine_init(MachineState *machine)
374{
375 const struct MemmapEntry *memmap = sifive_u_memmap;
376 SiFiveUState *s = RISCV_U_MACHINE(machine);
377 MemoryRegion *system_memory = get_system_memory();
378 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
379 MemoryRegion *flash0 = g_new(MemoryRegion, 1);
380 target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
7 *
8 * Provides a board compatible with the SiFive Freedom U SDK:

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373static void sifive_u_machine_init(MachineState *machine)
374{
375 const struct MemmapEntry *memmap = sifive_u_memmap;
376 SiFiveUState *s = RISCV_U_MACHINE(machine);
377 MemoryRegion *system_memory = get_system_memory();
378 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
379 MemoryRegion *flash0 = g_new(MemoryRegion, 1);
380 target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
381 uint32_t start_addr_hi32 = 0x00000000;
381 int i;
382 uint32_t fdt_load_addr;
383 uint64_t kernel_entry;
384
385 /* Initialize SoC */
386 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
387 object_property_set_uint(OBJECT(&s->soc), "serial", s->serial,
388 &error_abort);

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455 * if kernel argument is not set.
456 */
457 kernel_entry = 0;
458 }
459
460 /* Compute the fdt load address in dram */
461 fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base,
462 machine->ram_size, s->fdt);
382 int i;
383 uint32_t fdt_load_addr;
384 uint64_t kernel_entry;
385
386 /* Initialize SoC */
387 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
388 object_property_set_uint(OBJECT(&s->soc), "serial", s->serial,
389 &error_abort);

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456 * if kernel argument is not set.
457 */
458 kernel_entry = 0;
459 }
460
461 /* Compute the fdt load address in dram */
462 fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base,
463 machine->ram_size, s->fdt);
464 #if defined(TARGET_RISCV64)
465 start_addr_hi32 = start_addr >> 32;
466 #endif
463
464 /* reset vector */
465 uint32_t reset_vec[11] = {
466 s->msel, /* MSEL pin state */
467 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
468 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
469 0xf1402573, /* csrr a0, mhartid */
470#if defined(TARGET_RISCV32)
471 0x0202a583, /* lw a1, 32(t0) */
472 0x0182a283, /* lw t0, 24(t0) */
473#elif defined(TARGET_RISCV64)
474 0x0202b583, /* ld a1, 32(t0) */
475 0x0182b283, /* ld t0, 24(t0) */
476#endif
477 0x00028067, /* jr t0 */
478 start_addr, /* start: .dword */
467
468 /* reset vector */
469 uint32_t reset_vec[11] = {
470 s->msel, /* MSEL pin state */
471 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
472 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
473 0xf1402573, /* csrr a0, mhartid */
474#if defined(TARGET_RISCV32)
475 0x0202a583, /* lw a1, 32(t0) */
476 0x0182a283, /* lw t0, 24(t0) */
477#elif defined(TARGET_RISCV64)
478 0x0202b583, /* ld a1, 32(t0) */
479 0x0182b283, /* ld t0, 24(t0) */
480#endif
481 0x00028067, /* jr t0 */
482 start_addr, /* start: .dword */
479 0x00000000,
483 start_addr_hi32,
480 fdt_load_addr, /* fdt_laddr: .dword */
481 0x00000000,
482 /* fw_dyn: */
483 };
484
485 /* copy in the reset vector in little_endian byte order */
486 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
487 reset_vec[i] = cpu_to_le32(reset_vec[i]);

--- 274 unchanged lines hidden --- 		484 fdt_load_addr, /* fdt_laddr: .dword */
485 0x00000000,
486 /* fw_dyn: */
487 };
488
489 /* copy in the reset vector in little_endian byte order */
490 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
491 reset_vec[i] = cpu_to_le32(reset_vec[i]);

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