sifive_u.c (cb53b283b5adf4123273d07eee5e186e2e0a1b5b) sifive_u.c (7cfbb17f023dc014d366b2f30af852aa62a5c3b1)
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
7 *
8 * Provides a board compatible with the SiFive Freedom U SDK:

--- 84 unchanged lines hidden (view full) ---

93 MachineState *ms = MACHINE(qdev_get_machine());
94 void *fdt;
95 int cpu;
96 uint32_t *cells;
97 char *nodename;
98 uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
99 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
100 static const char * const ethclk_names[2] = { "pclk", "hclk" };
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
7 *
8 * Provides a board compatible with the SiFive Freedom U SDK:

--- 84 unchanged lines hidden (view full) ---

93 MachineState *ms = MACHINE(qdev_get_machine());
94 void *fdt;
95 int cpu;
96 uint32_t *cells;
97 char *nodename;
98 uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
99 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
100 static const char * const ethclk_names[2] = { "pclk", "hclk" };
101 static const char * const clint_compat[2] = {
102 "sifive,clint0", "riscv,clint0"
103 };
101
102 if (ms->dtb) {
103 fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size);
104 if (!fdt) {
105 error_report("load_device_tree() failed");
106 exit(1);
107 }
108 goto update_bootargs;

--- 95 unchanged lines hidden (view full) ---

204 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
205 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
206 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
207 g_free(nodename);
208 }
209 nodename = g_strdup_printf("/soc/clint@%lx",
210 (long)memmap[SIFIVE_U_DEV_CLINT].base);
211 qemu_fdt_add_subnode(fdt, nodename);
104
105 if (ms->dtb) {
106 fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size);
107 if (!fdt) {
108 error_report("load_device_tree() failed");
109 exit(1);
110 }
111 goto update_bootargs;

--- 95 unchanged lines hidden (view full) ---

207 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
208 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
209 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
210 g_free(nodename);
211 }
212 nodename = g_strdup_printf("/soc/clint@%lx",
213 (long)memmap[SIFIVE_U_DEV_CLINT].base);
214 qemu_fdt_add_subnode(fdt, nodename);
212 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
215 qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
216 (char **)&clint_compat, ARRAY_SIZE(clint_compat));
213 qemu_fdt_setprop_cells(fdt, nodename, "reg",
214 0x0, memmap[SIFIVE_U_DEV_CLINT].base,
215 0x0, memmap[SIFIVE_U_DEV_CLINT].size);
216 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
217 cells, ms->smp.cpus * sizeof(uint32_t) * 4);
218 g_free(cells);
219 g_free(nodename);
220

--- 728 unchanged lines hidden --- 		217 qemu_fdt_setprop_cells(fdt, nodename, "reg",
218 0x0, memmap[SIFIVE_U_DEV_CLINT].base,
219 0x0, memmap[SIFIVE_U_DEV_CLINT].size);
220 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
221 cells, ms->smp.cpus * sizeof(uint32_t) * 4);
222 g_free(cells);
223 g_free(nodename);
224

--- 728 unchanged lines hidden ---