sifive_u.c (c3a28b5d04f3b177befa1235e95e7bb09023f859) sifive_u.c (a6902ef0e3a83ea3dcf54f1919d485d4cf148506)
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
7 *
8 * Provides a board compatible with the SiFive Freedom U SDK:

--- 51 unchanged lines hidden (view full) ---

60
61static const struct MemmapEntry {
62 hwaddr base;
63 hwaddr size;
64} sifive_u_memmap[] = {
65 [SIFIVE_U_DEBUG] = { 0x0, 0x100 },
66 [SIFIVE_U_MROM] = { 0x1000, 0x11000 },
67 [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
7 *
8 * Provides a board compatible with the SiFive Freedom U SDK:

--- 51 unchanged lines hidden (view full) ---

60
61static const struct MemmapEntry {
62 hwaddr base;
63 hwaddr size;
64} sifive_u_memmap[] = {
65 [SIFIVE_U_DEBUG] = { 0x0, 0x100 },
66 [SIFIVE_U_MROM] = { 0x1000, 0x11000 },
67 [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
68 [SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 },
68 [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
69 [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
70 [SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
71 [SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
72 [SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
73 [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
74 [SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
75 [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },

--- 351 unchanged lines hidden (view full) ---

427
428static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
429{
430 MachineState *ms = MACHINE(qdev_get_machine());
431 SiFiveUSoCState *s = RISCV_U_SOC(dev);
432 const struct MemmapEntry *memmap = sifive_u_memmap;
433 MemoryRegion *system_memory = get_system_memory();
434 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
69 [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
70 [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
71 [SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
72 [SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
73 [SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
74 [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
75 [SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
76 [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },

--- 351 unchanged lines hidden (view full) ---

428
429static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
430{
431 MachineState *ms = MACHINE(qdev_get_machine());
432 SiFiveUSoCState *s = RISCV_U_SOC(dev);
433 const struct MemmapEntry *memmap = sifive_u_memmap;
434 MemoryRegion *system_memory = get_system_memory();
435 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
436 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
435 qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
436 char *plic_hart_config;
437 size_t plic_hart_config_len;
438 int i;
439 Error *err = NULL;
440 NICInfo *nd = &nd_table[0];
441
442 object_property_set_bool(OBJECT(&s->e_cpus), true, "realized",

--- 12 unchanged lines hidden (view full) ---

455 &error_abort);
456
457 /* boot rom */
458 memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom",
459 memmap[SIFIVE_U_MROM].size, &error_fatal);
460 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
461 mask_rom);
462
437 qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
438 char *plic_hart_config;
439 size_t plic_hart_config_len;
440 int i;
441 Error *err = NULL;
442 NICInfo *nd = &nd_table[0];
443
444 object_property_set_bool(OBJECT(&s->e_cpus), true, "realized",

--- 12 unchanged lines hidden (view full) ---

457 &error_abort);
458
459 /* boot rom */
460 memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom",
461 memmap[SIFIVE_U_MROM].size, &error_fatal);
462 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
463 mask_rom);
464
465 /*
466 * Add L2-LIM at reset size.
467 * This should be reduced in size as the L2 Cache Controller WayEnable
468 * register is incremented. Unfortunately I don't see a nice (or any) way
469 * to handle reducing or blocking out the L2 LIM while still allowing it
470 * be re returned to all enabled after a reset. For the time being, just
471 * leave it enabled all the time. This won't break anything, but will be
472 * too generous to misbehaving guests.
473 */
474 memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
475 memmap[SIFIVE_U_L2LIM].size, &error_fatal);
476 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base,
477 l2lim_mem);
478
463 /* create PLIC hart topology configuration string */
464 plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
465 ms->smp.cpus;
466 plic_hart_config = g_malloc0(plic_hart_config_len);
467 for (i = 0; i < ms->smp.cpus; i++) {
468 if (i != 0) {
469 strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
470 plic_hart_config_len);

--- 89 unchanged lines hidden --- 		479 /* create PLIC hart topology configuration string */
480 plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
481 ms->smp.cpus;
482 plic_hart_config = g_malloc0(plic_hart_config_len);
483 for (i = 0; i < ms->smp.cpus; i++) {
484 if (i != 0) {
485 strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
486 plic_hart_config_len);

--- 89 unchanged lines hidden ---