sifive_u.c (9bca0edb282de0007a4f068d9d20f3e3c3aadef7) sifive_u.c (2a8756ed7d64f8fed6ad50fb062f7118e47c856c)
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 *
7 * Provides a board compatible with the SiFive Freedom U SDK:
8 *

--- 108 unchanged lines hidden (view full) ---

117 qemu_fdt_add_subnode(fdt, nodename);
118 qemu_fdt_setprop_cells(fdt, nodename, "reg",
119 memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
120 mem_size >> 32, mem_size);
121 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
122 g_free(nodename);
123
124 qemu_fdt_add_subnode(fdt, "/cpus");
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 *
7 * Provides a board compatible with the SiFive Freedom U SDK:
8 *

--- 108 unchanged lines hidden (view full) ---

117 qemu_fdt_add_subnode(fdt, nodename);
118 qemu_fdt_setprop_cells(fdt, nodename, "reg",
119 memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
120 mem_size >> 32, mem_size);
121 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
122 g_free(nodename);
123
124 qemu_fdt_add_subnode(fdt, "/cpus");
125 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 10000000);
125 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
126 SIFIVE_CLINT_TIMEBASE_FREQ);
126 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
127 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
128
129 for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
130 nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
131 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
132 char *isa = riscv_isa_string(&s->soc.harts[cpu]);
133 qemu_fdt_add_subnode(fdt, nodename);
127 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
128 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
129
130 for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
131 nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
132 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
133 char *isa = riscv_isa_string(&s->soc.harts[cpu]);
134 qemu_fdt_add_subnode(fdt, nodename);
134 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 1000000000);
135 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
136 SIFIVE_U_CLOCK_FREQ);
135 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
136 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
137 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
138 qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
139 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
140 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
141 qemu_fdt_add_subnode(fdt, intc);
142 qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);

--- 197 unchanged lines hidden --- 		137 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
138 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
139 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
140 qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
141 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
142 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
143 qemu_fdt_add_subnode(fdt, intc);
144 qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);

--- 197 unchanged lines hidden ---