sifive_u.c (84fcf3c15111de9f0c72efbb6bc0def264555c46) sifive_u.c (b609b7e3199912e16ef3b0447823f21fed73597e)
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
7 *
8 * Provides a board compatible with the SiFive Freedom U SDK:

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41#include "hw/irq.h"
42#include "hw/loader.h"
43#include "hw/sysbus.h"
44#include "hw/char/serial.h"
45#include "hw/cpu/cluster.h"
46#include "hw/misc/unimp.h"
47#include "target/riscv/cpu.h"
48#include "hw/riscv/riscv_hart.h"
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
7 *
8 * Provides a board compatible with the SiFive Freedom U SDK:

--- 32 unchanged lines hidden (view full) ---

41#include "hw/irq.h"
42#include "hw/loader.h"
43#include "hw/sysbus.h"
44#include "hw/char/serial.h"
45#include "hw/cpu/cluster.h"
46#include "hw/misc/unimp.h"
47#include "target/riscv/cpu.h"
48#include "hw/riscv/riscv_hart.h"
49#include "hw/riscv/sifive_uart.h"
50#include "hw/riscv/sifive_u.h"
51#include "hw/riscv/boot.h"
49#include "hw/riscv/sifive_u.h"
50#include "hw/riscv/boot.h"
51#include "hw/char/sifive_uart.h"
52#include "hw/intc/sifive_clint.h"
53#include "hw/intc/sifive_plic.h"
54#include "chardev/char.h"
55#include "net/eth.h"
56#include "sysemu/arch_init.h"
57#include "sysemu/device_tree.h"
58#include "sysemu/runstate.h"
59#include "sysemu/sysemu.h"

--- 762 unchanged lines hidden --- 		52#include "hw/intc/sifive_clint.h"
53#include "hw/intc/sifive_plic.h"
54#include "chardev/char.h"
55#include "net/eth.h"
56#include "sysemu/arch_init.h"
57#include "sysemu/device_tree.h"
58#include "sysemu/runstate.h"
59#include "sysemu/sysemu.h"

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