| sifive_u.c (731340813fdb4cb8339edb8630e3f923b7d987ec) | sifive_u.c (91a3387dc42b261e95eb402bf7d043b3a043209c) |
|---|---|
| 1/* 2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017 SiFive, Inc. 6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> 7 * 8 * Provides a board compatible with the SiFive Freedom U SDK: --- 816 unchanged lines hidden (view full) --- 825 int i, j; 826 NICInfo *nd = &nd_table[0]; 827 828 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); 829 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); 830 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type); 831 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); 832 | 1/* 2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017 SiFive, Inc. 6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> 7 * 8 * Provides a board compatible with the SiFive Freedom U SDK: --- 816 unchanged lines hidden (view full) --- 825 int i, j; 826 NICInfo *nd = &nd_table[0]; 827 828 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); 829 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); 830 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type); 831 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); 832 |
| 833 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); 834 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); | 833 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_fatal); 834 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_fatal); |
| 835 /* 836 * The cluster must be realized after the RISC-V hart array container, 837 * as the container's CPU object is only created on realize, and the 838 * CPU must exist and have been parented into the cluster before the 839 * cluster is realized. 840 */ 841 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); 842 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); --- 168 unchanged lines hidden --- | 835 /* 836 * The cluster must be realized after the RISC-V hart array container, 837 * as the container's CPU object is only created on realize, and the 838 * CPU must exist and have been parented into the cluster before the 839 * cluster is realized. 840 */ 841 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); 842 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); --- 168 unchanged lines hidden --- |