sifive_u.c (722f1352b6c248ead94efd77ff5726aa0cba949b) sifive_u.c (732612856a8948a6ba1148322651743aa963b51c)
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
7 *
8 * Provides a board compatible with the SiFive Freedom U SDK:

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58#include "net/eth.h"
59#include "sysemu/arch_init.h"
60#include "sysemu/device_tree.h"
61#include "sysemu/runstate.h"
62#include "sysemu/sysemu.h"
63
64#include <libfdt.h>
65
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
7 *
8 * Provides a board compatible with the SiFive Freedom U SDK:

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58#include "net/eth.h"
59#include "sysemu/arch_init.h"
60#include "sysemu/device_tree.h"
61#include "sysemu/runstate.h"
62#include "sysemu/sysemu.h"
63
64#include <libfdt.h>
65
66static const struct MemmapEntry {
67 hwaddr base;
68 hwaddr size;
69} sifive_u_memmap[] = {
66static const MemMapEntry sifive_u_memmap[] = {
70 [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
71 [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
72 [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 },
73 [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 },
74 [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 },
75 [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 },
76 [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 },
77 [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 },

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86 [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 },
87 [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 },
88 [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 },
89};
90
91#define OTP_SERIAL 1
92#define GEM_REVISION 0x10070109
93
67 [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
68 [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
69 [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 },
70 [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 },
71 [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 },
72 [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 },
73 [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 },
74 [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 },

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83 [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 },
84 [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 },
85 [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 },
86};
87
88#define OTP_SERIAL 1
89#define GEM_REVISION 0x10070109
90
94static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
91static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
95 uint64_t mem_size, const char *cmdline, bool is_32_bit)
96{
97 MachineState *ms = MACHINE(qdev_get_machine());
98 void *fdt;
99 int cpu;
100 uint32_t *cells;
101 char *nodename;
102 char ethclk_names[] = "pclk\0hclk";

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479 /* gpio pin active low triggers reset */
480 if (!level) {
481 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
482 }
483}
484
485static void sifive_u_machine_init(MachineState *machine)
486{
92 uint64_t mem_size, const char *cmdline, bool is_32_bit)
93{
94 MachineState *ms = MACHINE(qdev_get_machine());
95 void *fdt;
96 int cpu;
97 uint32_t *cells;
98 char *nodename;
99 char ethclk_names[] = "pclk\0hclk";

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476 /* gpio pin active low triggers reset */
477 if (!level) {
478 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
479 }
480}
481
482static void sifive_u_machine_init(MachineState *machine)
483{
487 const struct MemmapEntry *memmap = sifive_u_memmap;
484 const MemMapEntry *memmap = sifive_u_memmap;
488 SiFiveUState *s = RISCV_U_MACHINE(machine);
489 MemoryRegion *system_memory = get_system_memory();
490 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
491 MemoryRegion *flash0 = g_new(MemoryRegion, 1);
492 target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
493 target_ulong firmware_end_addr, kernel_start_addr;
494 uint32_t start_addr_hi32 = 0x00000000;
495 int i;

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761 object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI);
762 object_initialize_child(obj, "spi2", &s->spi2, TYPE_SIFIVE_SPI);
763}
764
765static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
766{
767 MachineState *ms = MACHINE(qdev_get_machine());
768 SiFiveUSoCState *s = RISCV_U_SOC(dev);
485 SiFiveUState *s = RISCV_U_MACHINE(machine);
486 MemoryRegion *system_memory = get_system_memory();
487 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
488 MemoryRegion *flash0 = g_new(MemoryRegion, 1);
489 target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
490 target_ulong firmware_end_addr, kernel_start_addr;
491 uint32_t start_addr_hi32 = 0x00000000;
492 int i;

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758 object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI);
759 object_initialize_child(obj, "spi2", &s->spi2, TYPE_SIFIVE_SPI);
760}
761
762static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
763{
764 MachineState *ms = MACHINE(qdev_get_machine());
765 SiFiveUSoCState *s = RISCV_U_SOC(dev);
769 const struct MemmapEntry *memmap = sifive_u_memmap;
766 const MemMapEntry *memmap = sifive_u_memmap;
770 MemoryRegion *system_memory = get_system_memory();
771 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
772 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
773 char *plic_hart_config;
774 size_t plic_hart_config_len;
775 int i;
776 NICInfo *nd = &nd_table[0];
777

--- 175 unchanged lines hidden --- 		767 MemoryRegion *system_memory = get_system_memory();
768 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
769 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
770 char *plic_hart_config;
771 size_t plic_hart_config_len;
772 int i;
773 NICInfo *nd = &nd_table[0];
774

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