| sifive_u.c (4ecc984210ca1bf508a96a550ec8a93a5f833f6c) | sifive_u.c (bb8136df698bd565ee4f6c18d26c50dee320bfe4) |
|---|---|
| 1/* 2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017 SiFive, Inc. 6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> 7 * 8 * Provides a board compatible with the SiFive Freedom U SDK: --- 528 unchanged lines hidden (view full) --- 537 SIFIVE_U_PLIC_NUM_PRIORITIES, 538 SIFIVE_U_PLIC_PRIORITY_BASE, 539 SIFIVE_U_PLIC_PENDING_BASE, 540 SIFIVE_U_PLIC_ENABLE_BASE, 541 SIFIVE_U_PLIC_ENABLE_STRIDE, 542 SIFIVE_U_PLIC_CONTEXT_BASE, 543 SIFIVE_U_PLIC_CONTEXT_STRIDE, 544 memmap[SIFIVE_U_PLIC].size); | 1/* 2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017 SiFive, Inc. 6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> 7 * 8 * Provides a board compatible with the SiFive Freedom U SDK: --- 528 unchanged lines hidden (view full) --- 537 SIFIVE_U_PLIC_NUM_PRIORITIES, 538 SIFIVE_U_PLIC_PRIORITY_BASE, 539 SIFIVE_U_PLIC_PENDING_BASE, 540 SIFIVE_U_PLIC_ENABLE_BASE, 541 SIFIVE_U_PLIC_ENABLE_STRIDE, 542 SIFIVE_U_PLIC_CONTEXT_BASE, 543 SIFIVE_U_PLIC_CONTEXT_STRIDE, 544 memmap[SIFIVE_U_PLIC].size); |
| 545 g_free(plic_hart_config); |
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| 545 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, 546 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); 547 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, 548 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); 549 sifive_clint_create(memmap[SIFIVE_U_CLINT].base, 550 memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, 551 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); 552 --- 78 unchanged lines hidden --- | 546 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, 547 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); 548 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, 549 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); 550 sifive_clint_create(memmap[SIFIVE_U_CLINT].base, 551 memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, 552 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); 553 --- 78 unchanged lines hidden --- |