sifive_u.c (1b3a230870a9f9ef2bfb674e27e4935cdcb44aa5) sifive_u.c (687caef13d084b829156c7784a62d4c07316ae47)
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
7 *
8 * Provides a board compatible with the SiFive Freedom U SDK:

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306 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
307
308 g_free(nodename);
309}
310
311static void riscv_sifive_u_init(MachineState *machine)
312{
313 const struct MemmapEntry *memmap = sifive_u_memmap;
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
7 *
8 * Provides a board compatible with the SiFive Freedom U SDK:

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306 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
307
308 g_free(nodename);
309}
310
311static void riscv_sifive_u_init(MachineState *machine)
312{
313 const struct MemmapEntry *memmap = sifive_u_memmap;
314
315 SiFiveUState *s = g_new0(SiFiveUState, 1);
314 SiFiveUState *s = RISCV_U_MACHINE(machine);
316 MemoryRegion *system_memory = get_system_memory();
317 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
318 MemoryRegion *flash0 = g_new(MemoryRegion, 1);
319 int i;
320
321 /* Initialize SoC */
322 object_initialize_child(OBJECT(machine), "soc", &s->soc,
323 sizeof(s->soc), TYPE_RISCV_U_SOC,

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429 TYPE_SIFIVE_U_PRCI);
430 sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp),
431 TYPE_SIFIVE_U_OTP);
432 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", OTP_SERIAL);
433 sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
434 TYPE_CADENCE_GEM);
435}
436
315 MemoryRegion *system_memory = get_system_memory();
316 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
317 MemoryRegion *flash0 = g_new(MemoryRegion, 1);
318 int i;
319
320 /* Initialize SoC */
321 object_initialize_child(OBJECT(machine), "soc", &s->soc,
322 sizeof(s->soc), TYPE_RISCV_U_SOC,

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428 TYPE_SIFIVE_U_PRCI);
429 sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp),
430 TYPE_SIFIVE_U_OTP);
431 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", OTP_SERIAL);
432 sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
433 TYPE_CADENCE_GEM);
434}
435
436static void riscv_sifive_u_machine_instance_init(Object *obj)
437{
438}
439
437static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
438{
439 MachineState *ms = MACHINE(qdev_get_machine());
440 SiFiveUSoCState *s = RISCV_U_SOC(dev);
441 const struct MemmapEntry *memmap = sifive_u_memmap;
442 MemoryRegion *system_memory = get_system_memory();
443 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
444 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);

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542 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
543 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
544 plic_gpios[SIFIVE_U_GEM_IRQ]);
545
546 create_unimplemented_device("riscv.sifive.u.gem-mgmt",
547 memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
548}
549
440static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
441{
442 MachineState *ms = MACHINE(qdev_get_machine());
443 SiFiveUSoCState *s = RISCV_U_SOC(dev);
444 const struct MemmapEntry *memmap = sifive_u_memmap;
445 MemoryRegion *system_memory = get_system_memory();
446 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
447 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);

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545 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
546 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
547 plic_gpios[SIFIVE_U_GEM_IRQ]);
548
549 create_unimplemented_device("riscv.sifive.u.gem-mgmt",
550 memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
551}
552
550static void riscv_sifive_u_machine_init(MachineClass *mc)
551{
552 mc->desc = "RISC-V Board compatible with SiFive U SDK";
553 mc->init = riscv_sifive_u_init;
554 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
555 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
556 mc->default_cpus = mc->min_cpus;
557}
558
559DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
560
561static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
562{
563 DeviceClass *dc = DEVICE_CLASS(oc);
564
565 dc->realize = riscv_sifive_u_soc_realize;
566 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
567 dc->user_creatable = false;
568}

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576};
577
578static void riscv_sifive_u_soc_register_types(void)
579{
580 type_register_static(&riscv_sifive_u_soc_type_info);
581}
582
583type_init(riscv_sifive_u_soc_register_types)
553static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
554{
555 DeviceClass *dc = DEVICE_CLASS(oc);
556
557 dc->realize = riscv_sifive_u_soc_realize;
558 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
559 dc->user_creatable = false;
560}

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568};
569
570static void riscv_sifive_u_soc_register_types(void)
571{
572 type_register_static(&riscv_sifive_u_soc_type_info);
573}
574
575type_init(riscv_sifive_u_soc_register_types)
576
577static void riscv_sifive_u_machine_class_init(ObjectClass *oc, void *data)
578{
579 MachineClass *mc = MACHINE_CLASS(oc);
580
581 mc->desc = "RISC-V Board compatible with SiFive U SDK";
582 mc->init = riscv_sifive_u_init;
583 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
584 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
585 mc->default_cpus = mc->min_cpus;
586}
587
588static const TypeInfo riscv_sifive_u_machine_typeinfo = {
589 .name = MACHINE_TYPE_NAME("sifive_u"),
590 .parent = TYPE_MACHINE,
591 .class_init = riscv_sifive_u_machine_class_init,
592 .instance_init = riscv_sifive_u_machine_instance_init,
593 .instance_size = sizeof(SiFiveUState),
594};
595
596static void riscv_sifive_u_machine_init_register_types(void)
597{
598 type_register_static(&riscv_sifive_u_machine_typeinfo);
599}
600
601type_init(riscv_sifive_u_machine_init_register_types)