sifive_u.c (052e6534c49ebef8901824b77abc39271f0d852e) sifive_u.c (9d3f7108bc43e93ceef7faa27c87eea8295c33ed)
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
7 *
8 * Provides a board compatible with the SiFive Freedom U SDK:

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528static void sifive_u_machine_init(MachineState *machine)
529{
530 const MemMapEntry *memmap = sifive_u_memmap;
531 SiFiveUState *s = RISCV_U_MACHINE(machine);
532 MemoryRegion *system_memory = get_system_memory();
533 MemoryRegion *flash0 = g_new(MemoryRegion, 1);
534 target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
535 target_ulong firmware_end_addr, kernel_start_addr;
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
7 *
8 * Provides a board compatible with the SiFive Freedom U SDK:

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528static void sifive_u_machine_init(MachineState *machine)
529{
530 const MemMapEntry *memmap = sifive_u_memmap;
531 SiFiveUState *s = RISCV_U_MACHINE(machine);
532 MemoryRegion *system_memory = get_system_memory();
533 MemoryRegion *flash0 = g_new(MemoryRegion, 1);
534 target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
535 target_ulong firmware_end_addr, kernel_start_addr;
536 const char *firmware_name;
536 uint32_t start_addr_hi32 = 0x00000000;
537 int i;
538 uint32_t fdt_load_addr;
539 uint64_t kernel_entry;
540 DriveInfo *dinfo;
541 BlockBackend *blk;
542 DeviceState *flash_dev, *sd_dev, *card_dev;
543 qemu_irq flash_cs, sd_cs;

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590 case MSEL_L2LIM_QSPI2_SD:
591 start_addr = memmap[SIFIVE_U_DEV_L2LIM].base;
592 break;
593 default:
594 start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
595 break;
596 }
597
537 uint32_t start_addr_hi32 = 0x00000000;
538 int i;
539 uint32_t fdt_load_addr;
540 uint64_t kernel_entry;
541 DriveInfo *dinfo;
542 BlockBackend *blk;
543 DeviceState *flash_dev, *sd_dev, *card_dev;
544 qemu_irq flash_cs, sd_cs;

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591 case MSEL_L2LIM_QSPI2_SD:
592 start_addr = memmap[SIFIVE_U_DEV_L2LIM].base;
593 break;
594 default:
595 start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
596 break;
597 }
598
598 if (riscv_is_32bit(&s->soc.u_cpus)) {
599 firmware_end_addr = riscv_find_and_load_firmware(machine,
600 RISCV32_BIOS_BIN, start_addr, NULL);
601 } else {
602 firmware_end_addr = riscv_find_and_load_firmware(machine,
603 RISCV64_BIOS_BIN, start_addr, NULL);
604 }
599 firmware_name = riscv_default_firmware_name(&s->soc.u_cpus);
600 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
601 start_addr, NULL);
605
606 if (machine->kernel_filename) {
607 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
608 firmware_end_addr);
609
610 kernel_entry = riscv_load_kernel(machine->kernel_filename,
611 kernel_start_addr, NULL);
612

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603 if (machine->kernel_filename) {
604 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
605 firmware_end_addr);
606
607 kernel_entry = riscv_load_kernel(machine->kernel_filename,
608 kernel_start_addr, NULL);
609

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