sifive_e.c (afe33262585565b64df706c62b4b0f6e0ad30c71) sifive_e.c (91a3387dc42b261e95eb402bf7d043b3a043209c)
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom E SDK
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * Provides a board compatible with the SiFive Freedom E SDK:
7 *
8 * 0) UART

--- 181 unchanged lines hidden (view full) ---

190{
191 MachineState *ms = MACHINE(qdev_get_machine());
192 const MemMapEntry *memmap = sifive_e_memmap;
193 SiFiveESoCState *s = RISCV_E_SOC(dev);
194 MemoryRegion *sys_mem = get_system_memory();
195
196 object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
197 &error_abort);
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom E SDK
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * Provides a board compatible with the SiFive Freedom E SDK:
7 *
8 * 0) UART

--- 181 unchanged lines hidden (view full) ---

190{
191 MachineState *ms = MACHINE(qdev_get_machine());
192 const MemMapEntry *memmap = sifive_e_memmap;
193 SiFiveESoCState *s = RISCV_E_SOC(dev);
194 MemoryRegion *sys_mem = get_system_memory();
195
196 object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
197 &error_abort);
198 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
198 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
199
200 /* Mask ROM */
201 memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
202 memmap[SIFIVE_E_DEV_MROM].size, &error_fatal);
203 memory_region_add_subregion(sys_mem,
204 memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom);
205
206 /* MMIO */

--- 88 unchanged lines hidden --- 		199
200 /* Mask ROM */
201 memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
202 memmap[SIFIVE_E_DEV_MROM].size, &error_fatal);
203 memory_region_add_subregion(sys_mem,
204 memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom);
205
206 /* MMIO */

--- 88 unchanged lines hidden ---