sifive_e.c (9fc7fc4d3909817555ce0af6bcb69dff1606140d) sifive_e.c (db873cc5d1a4aaa67eea87768d504b2f89d88738)
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom E SDK
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * Provides a board compatible with the SiFive Freedom E SDK:
7 *
8 * 0) UART

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142
143type_init(sifive_e_machine_init_register_types)
144
145static void riscv_sifive_e_soc_init(Object *obj)
146{
147 MachineState *ms = MACHINE(qdev_get_machine());
148 SiFiveESoCState *s = RISCV_E_SOC(obj);
149
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom E SDK
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * Provides a board compatible with the SiFive Freedom E SDK:
7 *
8 * 0) UART

--- 133 unchanged lines hidden (view full) ---

142
143type_init(sifive_e_machine_init_register_types)
144
145static void riscv_sifive_e_soc_init(Object *obj)
146{
147 MachineState *ms = MACHINE(qdev_get_machine());
148 SiFiveESoCState *s = RISCV_E_SOC(obj);
149
150 sysbus_init_child_obj(obj, "cpus", &s->cpus,
151 sizeof(s->cpus), TYPE_RISCV_HART_ARRAY);
150 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
152 object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
153 &error_abort);
151 object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
152 &error_abort);
154 sysbus_init_child_obj(obj, "riscv.sifive.e.gpio0",
155 &s->gpio, sizeof(s->gpio),
156 TYPE_SIFIVE_GPIO);
153 object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
154 TYPE_SIFIVE_GPIO);
157}
158
159static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
160{
161 MachineState *ms = MACHINE(qdev_get_machine());
162 const struct MemmapEntry *memmap = sifive_e_memmap;
163 Error *err = NULL;
164
165 SiFiveESoCState *s = RISCV_E_SOC(dev);
166 MemoryRegion *sys_mem = get_system_memory();
167
168 object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type",
169 &error_abort);
155}
156
157static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
158{
159 MachineState *ms = MACHINE(qdev_get_machine());
160 const struct MemmapEntry *memmap = sifive_e_memmap;
161 Error *err = NULL;
162
163 SiFiveESoCState *s = RISCV_E_SOC(dev);
164 MemoryRegion *sys_mem = get_system_memory();
165
166 object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type",
167 &error_abort);
170 object_property_set_bool(OBJECT(&s->cpus), true, "realized",
171 &error_abort);
168 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
172
173 /* Mask ROM */
174 memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
175 memmap[SIFIVE_E_MROM].size, &error_fatal);
176 memory_region_add_subregion(sys_mem,
177 memmap[SIFIVE_E_MROM].base, &s->mask_rom);
178
179 /* MMIO */

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192 memmap[SIFIVE_E_CLINT].size, ms->smp.cpus,
193 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
194 create_unimplemented_device("riscv.sifive.e.aon",
195 memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
196 sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
197
198 /* GPIO */
199
169
170 /* Mask ROM */
171 memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
172 memmap[SIFIVE_E_MROM].size, &error_fatal);
173 memory_region_add_subregion(sys_mem,
174 memmap[SIFIVE_E_MROM].base, &s->mask_rom);
175
176 /* MMIO */

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189 memmap[SIFIVE_E_CLINT].size, ms->smp.cpus,
190 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
191 create_unimplemented_device("riscv.sifive.e.aon",
192 memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
193 sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
194
195 /* GPIO */
196
200 object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
197 sysbus_realize(SYS_BUS_DEVICE(&s->gpio), &err);
201 if (err) {
202 error_propagate(errp, err);
203 return;
204 }
205
206 /* Map GPIO registers */
207 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_GPIO0].base);
208

--- 57 unchanged lines hidden --- 		198 if (err) {
199 error_propagate(errp, err);
200 return;
201 }
202
203 /* Map GPIO registers */
204 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_GPIO0].base);
205

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