sifive_e.c (651cd8b7e18eda46a36cf073428452d04bb354f2) sifive_e.c (647a70a10f257bdeba33ff5f1bcb2b26518a9f4c)
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom E SDK
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * Provides a board compatible with the SiFive Freedom E SDK:
7 *
8 * 0) UART

--- 173 unchanged lines hidden (view full) ---

182 memmap[SIFIVE_E_CLINT].size, smp_cpus,
183 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
184 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon",
185 memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
186 sifive_prci_create(memmap[SIFIVE_E_PRCI].base);
187 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.gpio0",
188 memmap[SIFIVE_E_GPIO0].base, memmap[SIFIVE_E_GPIO0].size);
189 sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base,
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom E SDK
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * Provides a board compatible with the SiFive Freedom E SDK:
7 *
8 * 0) UART

--- 173 unchanged lines hidden (view full) ---

182 memmap[SIFIVE_E_CLINT].size, smp_cpus,
183 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
184 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon",
185 memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
186 sifive_prci_create(memmap[SIFIVE_E_PRCI].base);
187 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.gpio0",
188 memmap[SIFIVE_E_GPIO0].base, memmap[SIFIVE_E_GPIO0].size);
189 sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base,
190 serial_hd(0), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_E_UART0_IRQ]);
190 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));
191 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi0",
192 memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size);
193 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0",
194 memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size);
195 /* sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base,
191 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi0",
192 memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size);
193 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0",
194 memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size);
195 /* sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base,
196 serial_hd(1), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_E_UART1_IRQ]); */
196 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic),
197 SIFIVE_E_UART1_IRQ)); */
197 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1",
198 memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size);
199 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1",
200 memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size);
201 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi2",
202 memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size);
203 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm2",
204 memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size);

--- 40 unchanged lines hidden --- 		198 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1",
199 memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size);
200 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1",
201 memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size);
202 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi2",
203 memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size);
204 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm2",
205 memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size);

--- 40 unchanged lines hidden ---