sifive_e.c (288a1cc6345ed0b04e0dc887905ebeef17141608) sifive_e.c (732612856a8948a6ba1148322651743aa963b51c)
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom E SDK
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * Provides a board compatible with the SiFive Freedom E SDK:
7 *
8 * 0) UART

--- 36 unchanged lines hidden (view full) ---

45#include "hw/intc/sifive_clint.h"
46#include "hw/intc/sifive_plic.h"
47#include "hw/misc/sifive_e_prci.h"
48#include "chardev/char.h"
49#include "sysemu/arch_init.h"
50#include "sysemu/sysemu.h"
51#include "exec/address-spaces.h"
52
1/*
2 * QEMU RISC-V Board Compatible with SiFive Freedom E SDK
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * Provides a board compatible with the SiFive Freedom E SDK:
7 *
8 * 0) UART

--- 36 unchanged lines hidden (view full) ---

45#include "hw/intc/sifive_clint.h"
46#include "hw/intc/sifive_plic.h"
47#include "hw/misc/sifive_e_prci.h"
48#include "chardev/char.h"
49#include "sysemu/arch_init.h"
50#include "sysemu/sysemu.h"
51#include "exec/address-spaces.h"
52
53static const struct MemmapEntry {
54 hwaddr base;
55 hwaddr size;
56} sifive_e_memmap[] = {
53static MemMapEntry sifive_e_memmap[] = {
57 [SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 },
58 [SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 },
59 [SIFIVE_E_DEV_OTP] = { 0x20000, 0x2000 },
60 [SIFIVE_E_DEV_CLINT] = { 0x2000000, 0x10000 },
61 [SIFIVE_E_DEV_PLIC] = { 0xc000000, 0x4000000 },
62 [SIFIVE_E_DEV_AON] = { 0x10000000, 0x8000 },
63 [SIFIVE_E_DEV_PRCI] = { 0x10008000, 0x8000 },
64 [SIFIVE_E_DEV_OTP_CTRL] = { 0x10010000, 0x1000 },

--- 7 unchanged lines hidden (view full) ---

72 [SIFIVE_E_DEV_QSPI2] = { 0x10034000, 0x1000 },
73 [SIFIVE_E_DEV_PWM2] = { 0x10035000, 0x1000 },
74 [SIFIVE_E_DEV_XIP] = { 0x20000000, 0x20000000 },
75 [SIFIVE_E_DEV_DTIM] = { 0x80000000, 0x4000 }
76};
77
78static void sifive_e_machine_init(MachineState *machine)
79{
54 [SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 },
55 [SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 },
56 [SIFIVE_E_DEV_OTP] = { 0x20000, 0x2000 },
57 [SIFIVE_E_DEV_CLINT] = { 0x2000000, 0x10000 },
58 [SIFIVE_E_DEV_PLIC] = { 0xc000000, 0x4000000 },
59 [SIFIVE_E_DEV_AON] = { 0x10000000, 0x8000 },
60 [SIFIVE_E_DEV_PRCI] = { 0x10008000, 0x8000 },
61 [SIFIVE_E_DEV_OTP_CTRL] = { 0x10010000, 0x1000 },

--- 7 unchanged lines hidden (view full) ---

69 [SIFIVE_E_DEV_QSPI2] = { 0x10034000, 0x1000 },
70 [SIFIVE_E_DEV_PWM2] = { 0x10035000, 0x1000 },
71 [SIFIVE_E_DEV_XIP] = { 0x20000000, 0x20000000 },
72 [SIFIVE_E_DEV_DTIM] = { 0x80000000, 0x4000 }
73};
74
75static void sifive_e_machine_init(MachineState *machine)
76{
80 const struct MemmapEntry *memmap = sifive_e_memmap;
77 const MemMapEntry *memmap = sifive_e_memmap;
81
82 SiFiveEState *s = RISCV_E_MACHINE(machine);
83 MemoryRegion *sys_mem = get_system_memory();
84 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
85 int i;
86
87 /* Initialize SoC */
88 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC);

--- 93 unchanged lines hidden (view full) ---

182 object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort);
183 object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
184 TYPE_SIFIVE_GPIO);
185}
186
187static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
188{
189 MachineState *ms = MACHINE(qdev_get_machine());
78
79 SiFiveEState *s = RISCV_E_MACHINE(machine);
80 MemoryRegion *sys_mem = get_system_memory();
81 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
82 int i;
83
84 /* Initialize SoC */
85 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC);

--- 93 unchanged lines hidden (view full) ---

179 object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort);
180 object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
181 TYPE_SIFIVE_GPIO);
182}
183
184static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
185{
186 MachineState *ms = MACHINE(qdev_get_machine());
190 const struct MemmapEntry *memmap = sifive_e_memmap;
187 const MemMapEntry *memmap = sifive_e_memmap;
191 SiFiveESoCState *s = RISCV_E_SOC(dev);
192 MemoryRegion *sys_mem = get_system_memory();
193
194 object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
195 &error_abort);
196 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
197
198 /* Mask ROM */

--- 91 unchanged lines hidden --- 		188 SiFiveESoCState *s = RISCV_E_SOC(dev);
189 MemoryRegion *sys_mem = get_system_memory();
190
191 object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
192 &error_abort);
193 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
194
195 /* Mask ROM */

--- 91 unchanged lines hidden ---