opentitan.c (a05f8ecd88f15273d033b6f044b850a8af84a5b8) opentitan.c (732612856a8948a6ba1148322651743aa963b51c)
1/*
2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
3 *
4 * Copyright (c) 2020 Western Digital
5 *
6 * Provides a board compatible with the OpenTitan FPGA platform:
7 *
8 * This program is free software; you can redistribute it and/or modify it

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23#include "qapi/error.h"
24#include "hw/boards.h"
25#include "hw/misc/unimp.h"
26#include "hw/riscv/boot.h"
27#include "exec/address-spaces.h"
28#include "qemu/units.h"
29#include "sysemu/sysemu.h"
30
1/*
2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
3 *
4 * Copyright (c) 2020 Western Digital
5 *
6 * Provides a board compatible with the OpenTitan FPGA platform:
7 *
8 * This program is free software; you can redistribute it and/or modify it

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23#include "qapi/error.h"
24#include "hw/boards.h"
25#include "hw/misc/unimp.h"
26#include "hw/riscv/boot.h"
27#include "exec/address-spaces.h"
28#include "qemu/units.h"
29#include "sysemu/sysemu.h"
30
31static const struct MemmapEntry {
32 hwaddr base;
33 hwaddr size;
34} ibex_memmap[] = {
31static const MemMapEntry ibex_memmap[] = {
35 [IBEX_DEV_ROM] = { 0x00008000, 16 * KiB },
36 [IBEX_DEV_RAM] = { 0x10000000, 0x10000 },
37 [IBEX_DEV_FLASH] = { 0x20000000, 0x80000 },
38 [IBEX_DEV_UART] = { 0x40000000, 0x1000 },
39 [IBEX_DEV_GPIO] = { 0x40040000, 0x1000 },
40 [IBEX_DEV_SPI] = { 0x40050000, 0x1000 },
41 [IBEX_DEV_I2C] = { 0x40080000, 0x1000 },
42 [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 },

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61 [IBEX_DEV_EDN1] = { 0x41180000, 0x1000 },
62 [IBEX_DEV_ALERT_HANDLER] = { 0x411b0000, 0x1000 },
63 [IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 },
64 [IBEX_DEV_OTBN] = { 0x411d0000, 0x10000 },
65};
66
67static void opentitan_board_init(MachineState *machine)
68{
32 [IBEX_DEV_ROM] = { 0x00008000, 16 * KiB },
33 [IBEX_DEV_RAM] = { 0x10000000, 0x10000 },
34 [IBEX_DEV_FLASH] = { 0x20000000, 0x80000 },
35 [IBEX_DEV_UART] = { 0x40000000, 0x1000 },
36 [IBEX_DEV_GPIO] = { 0x40040000, 0x1000 },
37 [IBEX_DEV_SPI] = { 0x40050000, 0x1000 },
38 [IBEX_DEV_I2C] = { 0x40080000, 0x1000 },
39 [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 },

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58 [IBEX_DEV_EDN1] = { 0x41180000, 0x1000 },
59 [IBEX_DEV_ALERT_HANDLER] = { 0x411b0000, 0x1000 },
60 [IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 },
61 [IBEX_DEV_OTBN] = { 0x411d0000, 0x10000 },
62};
63
64static void opentitan_board_init(MachineState *machine)
65{
69 const struct MemmapEntry *memmap = ibex_memmap;
66 const MemMapEntry *memmap = ibex_memmap;
70 OpenTitanState *s = g_new0(OpenTitanState, 1);
71 MemoryRegion *sys_mem = get_system_memory();
72 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
73
74 /* Initialize SoC */
75 object_initialize_child(OBJECT(machine), "soc", &s->soc,
76 TYPE_RISCV_IBEX_SOC);
77 qdev_realize(DEVICE(&s->soc), NULL, &error_abort);

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109
110 object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC);
111
112 object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
113}
114
115static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
116{
67 OpenTitanState *s = g_new0(OpenTitanState, 1);
68 MemoryRegion *sys_mem = get_system_memory();
69 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
70
71 /* Initialize SoC */
72 object_initialize_child(OBJECT(machine), "soc", &s->soc,
73 TYPE_RISCV_IBEX_SOC);
74 qdev_realize(DEVICE(&s->soc), NULL, &error_abort);

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106
107 object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC);
108
109 object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
110}
111
112static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
113{
117 const struct MemmapEntry *memmap = ibex_memmap;
114 const MemMapEntry *memmap = ibex_memmap;
118 MachineState *ms = MACHINE(qdev_get_machine());
119 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
120 MemoryRegion *sys_mem = get_system_memory();
121
122 object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
123 &error_abort);
124 object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
125 &error_abort);

--- 115 unchanged lines hidden --- 		115 MachineState *ms = MACHINE(qdev_get_machine());
116 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
117 MemoryRegion *sys_mem = get_system_memory();
118
119 object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
120 &error_abort);
121 object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
122 &error_abort);

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