opentitan.c (9fc7fc4d3909817555ce0af6bcb69dff1606140d) opentitan.c (db873cc5d1a4aaa67eea87768d504b2f89d88738)
1/*
2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
3 *
4 * Copyright (c) 2020 Western Digital
5 *
6 * Provides a board compatible with the OpenTitan FPGA platform:
7 *
8 * This program is free software; you can redistribute it and/or modify it

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88}
89
90DEFINE_MACHINE("opentitan", riscv_opentitan_machine_init)
91
92static void riscv_lowrisc_ibex_soc_init(Object *obj)
93{
94 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
95
1/*
2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
3 *
4 * Copyright (c) 2020 Western Digital
5 *
6 * Provides a board compatible with the OpenTitan FPGA platform:
7 *
8 * This program is free software; you can redistribute it and/or modify it

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88}
89
90DEFINE_MACHINE("opentitan", riscv_opentitan_machine_init)
91
92static void riscv_lowrisc_ibex_soc_init(Object *obj)
93{
94 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
95
96 sysbus_init_child_obj(obj, "cpus", &s->cpus,
97 sizeof(s->cpus), TYPE_RISCV_HART_ARRAY);
96 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
98}
99
100static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
101{
102 const struct MemmapEntry *memmap = ibex_memmap;
103 MachineState *ms = MACHINE(qdev_get_machine());
104 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
105 MemoryRegion *sys_mem = get_system_memory();
106
107 object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type",
108 &error_abort);
109 object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
110 &error_abort);
97}
98
99static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
100{
101 const struct MemmapEntry *memmap = ibex_memmap;
102 MachineState *ms = MACHINE(qdev_get_machine());
103 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
104 MemoryRegion *sys_mem = get_system_memory();
105
106 object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type",
107 &error_abort);
108 object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
109 &error_abort);
111 object_property_set_bool(OBJECT(&s->cpus), true, "realized",
112 &error_abort);
110 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
113
114 /* Boot ROM */
115 memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
116 memmap[IBEX_ROM].size, &error_fatal);
117 memory_region_add_subregion(sys_mem,
118 memmap[IBEX_ROM].base, &s->rom);
119
120 /* Flash memory */

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112 /* Boot ROM */
113 memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
114 memmap[IBEX_ROM].size, &error_fatal);
115 memory_region_add_subregion(sys_mem,
116 memmap[IBEX_ROM].base, &s->rom);
117
118 /* Flash memory */

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