opentitan.c (5d7e601df37d8bdd490472fd4cfe3e4ca258df09) opentitan.c (55c136599f512a86e3fec9f77b6b5a30a6b34cca)
1/*
2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
3 *
4 * Copyright (c) 2020 Western Digital
5 *
6 * Provides a board compatible with the OpenTitan FPGA platform:
7 *
8 * This program is free software; you can redistribute it and/or modify it

--- 84 unchanged lines hidden (view full) ---

93 object_initialize_child(OBJECT(machine), "soc", &s->soc,
94 TYPE_RISCV_IBEX_SOC);
95 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
96
97 memory_region_add_subregion(sys_mem,
98 memmap[IBEX_DEV_RAM].base, machine->ram);
99
100 if (machine->firmware) {
1/*
2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
3 *
4 * Copyright (c) 2020 Western Digital
5 *
6 * Provides a board compatible with the OpenTitan FPGA platform:
7 *
8 * This program is free software; you can redistribute it and/or modify it

--- 84 unchanged lines hidden (view full) ---

93 object_initialize_child(OBJECT(machine), "soc", &s->soc,
94 TYPE_RISCV_IBEX_SOC);
95 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
96
97 memory_region_add_subregion(sys_mem,
98 memmap[IBEX_DEV_RAM].base, machine->ram);
99
100 if (machine->firmware) {
101 riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL);
101 hwaddr firmware_load_addr = memmap[IBEX_DEV_RAM].base;
102 riscv_load_firmware(machine->firmware, &firmware_load_addr, NULL);
102 }
103
104 if (machine->kernel_filename) {
105 riscv_load_kernel(machine, &s->soc.cpus,
106 memmap[IBEX_DEV_RAM].base,
107 false, NULL);
108 }
109}

--- 229 unchanged lines hidden --- 		103 }
104
105 if (machine->kernel_filename) {
106 riscv_load_kernel(machine, &s->soc.cpus,
107 memmap[IBEX_DEV_RAM].base,
108 false, NULL);
109 }
110}

--- 229 unchanged lines hidden ---